Search Results for "chip"

Integrated component-based and cellular automata (CA) Parallel DEVS simulator: https://acims.asu.edu/devs-suite/ OFFERS: 1) synchronized execution & animation, 2) run-time linear/superdense I/O & state trajectories, 3) Action Level Real-Time modeling & simulation, 4) model checking, 5) ABM, 6) CA & composable CA playback, 7) KIB interaction modeling, 8) hierarchical model libraries, 9) Black-Box testing & debugging, 10) PostgreSQL repository, 11) FMU (OpenModelica), 12) OSATE (AADL)...

A networks-on-chip (NoC) simulator allows designers to early estimate performance (latency and throughput), energy efficiency (average/peak power, average energy per packet) and area of several networks on-chip configurations at different CMOS nodes. This tool is a cycle-accurate simulator and is open-source using SystemC, a C++ plugin, which is used to quickly model complex systems at a higher level but less details than RTL.

gpNoCsim++ is a Network-on-Chip simulator based on gpNoCsim that extends the gpNoCsim and adds new features such as: asynchroniztion (using multithreading), loading network traffic from file, new topologies(i.e WK-Recursive), GUI and reporting features.

A new simalator for Network-on-Chip which takes advantage of MPI.

Using SystemC to develop a System On Chip system. The Design includes a MIPS CPU, Arbiter, DMA controller, SRAM controller, UART controller. This design are compatible to the IBM CoreConnect™ Architecture and the On-chip Peripheral Bus (OPB) standard.