Search Results for "open systemc"
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Showing 31 open source projects for "open systemc"
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SystemC Network Simulation Library (SCNSL) is an extension of SystemC to allow modelling packet-based networks such as wireless networks, ethernet, fieldbus, etc. As done by basic SystemC for signals on the bus, SCNSL provides primitives to model packet trasmission, reception, contention on the channel and wireless path loss. The use of SCNSL allows the easy and complete modelling of distributed applications of networked embedded systems such as wireless sensor networks, routers...
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VlibTools
Tools and libraries for use with systemc and verilog
Tool suite and libraries for developing system-c models. Tools for managing RTL projects. -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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S2CBench
Synthesizable SystemC Benchmark Suite
S2CBench v.2.0 provides 18 programs written in synthesizable SystemC language. Each benchmark is designed for specific domains such as multimedia, digital signal processing, security, image processing, etc. The programs are provided with the objective to enable researchers analyze their innovative algorithms and techniques and help users compare the quality of results of state of the art commercial High Level Synthesis tools available in industry. You can log in to our Youtube channel... -
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SystemC-WMS (Wave Mixed Signal Simulator) is a class library that extends the standard SystemC kernel to allow modeling and simulation of complex systems comprising analog parts from heterogeneous domain (electrical, mechanical, thermal, ...).
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S3CBench
Synthesizable Security SystemC Benchmarks for High-Level Synthesis
Open source benchmark suite of synthesizable behavioral descriptions with different types of Hardware Trojan -
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PKtool is a SystemC/C++ environment dedicated to the power estimation for digital systems described in SystemC.
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ArchC is an open-source architecture description language based on SystemC. Its goal is to provide designers with a tool to evaluate new ideas in processor and ISA design, memory hierarchy, etc. and other aspects of computer architecture research.
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NOCEXplore
Network-on-Chip design exploration tool based on SystemC.
NOCEXplore is a Network-on-Chip design exploration tool based on SystemC. It includes libraries and executables for easy and fast upgradeable NoC models and a set of shell scripts. The project started during the PhD of Stefano Gigli at DII of Universita' Politecnica delle Marche (http://www.dii.univpm.it/) under the supervision of Prof. Massimo Conti and contribution of several students. -
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HSOC
Heterogeneous System-on-Chip Platform
HSoC is a open source, SystemC-based, cycle-accurate virtual platform for heterogeneous shared memory-based multicore SoCs. Each HSoC component has a clean interface, implements a separate class, and includes regression tests. Large-scale models can be instantiated, by connecting objects from all HSoC libraries. Each object may collect data by invoking a monitoring library. The target users are CS/EE professionals. Some experience with SoC design methodology and SystemC (e.g. reading... -
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NoCTweak
a Parameterizable Simulator for Early Exploration of Networks On-Chip
A networks-on-chip (NoC) simulator allows designers to early estimate performance (latency and throughput), energy efficiency (average/peak power, average energy per packet) and area of several networks on-chip configurations at different CMOS nodes. This tool is a cycle-accurate simulator and is open-source using SystemC, a C++ plugin, which is used to quickly model complex systems at a higher level but less details than RTL. NoCTweak was developed by Dr. Anh Tran and Dr. Bevan Baas at UC... -
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
... testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation) -
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Powersim
Energy Estimation in SystemC.
Power/Energy simulation in SystemC. Powersim is a SystemC class library aimed to the calculation of power and energy consumption of hardware described at system level. To this end C++ operators are monitored and different energy models can be used for each data type. Powersim does not require any change in the application source code. Current version is 0.3.0. -
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The Sampa library is a comprehensive C++ library and lua toolset to simulate and analyze system on chip architectures through fast cycle accurate transactional level simulation. Tags: ESL, SoC, NoC, TLM, interconnect, IP, SystemC. More on sampalib.org
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Open source high-level synthesis system developed within the FP7 OSMOSIS project. Includes gcc-based SystemC front-end, database with browsing GUI, scheduler/allocator/binder, and Verilog back-end. (We are under migration to SVN server now)
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SCLive is a modular Linux-Live Distribution dedicated to the OSCI SystemC simulator and it's associated libraries. The distribution provides a fully working environement including a simulator kernel, wavefom viewer, IDE, tutorials and more.
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s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.
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HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
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Sister is high-level synthesizer for SoC design . It analyzes SystemC(based on C++ language) source code and creates Verilog HDL source code.
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gscc stands for GNU SystemC Compiler Collection, witch is a set of tools to manipulate systemc code ( systemc is a hardware description language www.systemc.org ). The most notable tool is called gsc, witch is a systemc to verilog translator.
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HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
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A Hardware/Software Co-Simulation package utilizing TCP/IP networking to allow C and Perl based development simulation environments using Verilog or SystemC hardware models.
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