Search Results for "syntax tool"
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Showing 11 open source projects for "syntax tool"
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CAIRO for AERMOD
AERMOD, visualisation, input, modelling and compiling tool
CAIRO for AERMOD v1.1 by MSc Dominik Subotić Simplified training software Avaliable: www.sourceforge.net/projects/cairo-for-aermod/ QGIS plugin: CAIROforAERMOD (Coming 2025.) Tutorial: https://www.youtube.com/watch?v=DZnsJuu1zLc AERMAP, AERMOD and AERPLOT analysis tool and input file compiler. Features: Automatic input by copying coordinates (Google Maps or text) and automatic conversion to UTM. Sources are automatically visualised in Google Earth. Input is done through user interface and automatically compiled into correct syntax and project/file structure. Windows application, supports up to 3 averaging periods, maxtable, maxifile, rankfile and plotfile. ... -
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Canvas-2DGC
A user-extensible Freemat based 1DGC and GCxGC data analysis software.
Canvas-2DGC is a user-extensible, Freemat based 1DGC and comprehensive 2DGC (GCxGC) data visualization and processing software. GCxGC-MS data analysis is supported for Agilent GCMS data format. The first goal of this project is to provide a highly intelligent analytical tool for reducing a complex chromatographic data analysis, either 1D or 2D, to just a few simple and intuitive steps. The second goal is to provide a fast and practical way of customizing or extending functionalities by ordinary users through high-level Freemat scripting. Freemat, one of open source Matlab clones, is chosen for this very purpose, because its syntax is most compatible with Matlab and it is lightweight - very suited for ordinary users. ... -
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Scripted Roulette
Simulation tool for the casino game Roulette
Scripted Roulette is an original application which helps you to develop and analyze new betting strategies for the casino game Roulette. Learn and understand more about the chances you really have to win. -
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vHDL Obfuscator GUI
vHDL Obfuscator is an small GUI to obfuscate and reformat HDL files
VHDL and Verilog HDL are standards languages for hardware description. Sometimes is necessary to share the source HDL file but maintaining a little level of control and protection of the intellectual property. This tool generate obfuscated code that is almost unreadable to humans, but is still readable to compilers and simulators. This tool use GHDL (https://sourceforge.net/projects/ghdl-updates/), HDLObf (https://sourceforge.net/projects/hdlobf/), Icarus Verilog... -
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic... -
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A tool to support data-analysis on a Oracle-DB. In Greek mythology, Metis (Μῆτις) was of the Titan generation ... The Stoic commentators allegorized Metis as the embodiment of "wisdom" or "wise counsel" ... (from Wikipadia)
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Language Constructor
Complete tool for constructing/manipulating languages in digital form
With this tool you can easily design a new language, digitize an existing one or incrementally reconstruct an ancient language. It allows for free experimentation of all aspects of the language, so it does not have to be made consistent on paper first. You can edit script, syntax, grammar, morphology, lexicon and phonology, as well as write documents in the language, as it might be too complex to be handled by current font technology. -
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FPGAsm
Create fast bare-metal FPGA designs without Verilog or VHDL
FPGAsm is a low-level alternative to verilog and VHDL. A near-instant 'assembler for FPGAs', this simple yet powerful language facilitates bottom-up design, layout and wiring of modules, and generation of .xdl output. With about 10 keywords to learn, you can start making circuits in minutes. Now you can focus on learning the ins and outs of the FPGA instead of complex tools and languages. Fast turnaround time and bottom-up approach invite exploration, experimentation, live circuit... -
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The fast2armc program translates source code of a counter automata model for FAST(er) tool to the ARMC prolog syntax.
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AI-powered service management for IT and enterprise teamsGive your IT, operations, and business teams the ability to deliver exceptional services—without the complexity. Maximize operational efficiency with refreshingly simple, AI-powered Freshservice.
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Release 1 of BroadBit Test Tool (BTT) offers the power and efficiency of TTCN testing; all software testing engineers can add this platform independent tool it into their toolbox. Training support is available through training@broadbit.com.
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Geographic tag manipulator - a simple XSLT-based tool to add, remove, or change tags of OpenStreetMap objects.
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