Search Results for "open-lates"
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Showing 81 open source projects for "open-lates"
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a code... -
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Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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pyrpl
PyRPL turns your Red Pitaya into a powerful analog feedback device.
The Red Pitaya is a commercial, affordable FPGA board with fast analog inputs and outputs. This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, PyRPL (Python RedPitaya Lockbox) implements many devices that are needed for optics experiments with the Red Pitaya. PyRPL implements various digital signal processing (DSP) modules (see features below). It allows... -
Define and Deliver Comprehensive Cybersecurity Services. Security threats continue to grow, and your clients are most likely at risk. Small- to medium-sized businesses (SMBs) are targeted by 64% of all cyberattacks, and 62% of them admit lacking in-house expertise to deal with security issues. Now technology solution providers (TSPs) are a prime target. Enter ConnectWise Cybersecurity Management (formerly ConnectWise Fortify) — the advanced cybersecurity solution you need to deliver the managed detection and response protection your clients require. Whether you’re talking to prospects or clients, we provide you with the right insights and data to support your cybersecurity conversation. From client-facing reports to technical guidance, we reduce the noise by guiding you through what’s really needed to demonstrate the value of enhanced strategy.
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VlibTools
Tools and libraries for use with systemc and verilog
Tool suite and libraries for developing system-c models. Tools for managing RTL projects. -
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vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.
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Docubee is an intelligent contract automation platform that allows you to quickly and painlessly generate, manage, share, and sign contracts. Featuring powerful conditional logic-based workflows, generative AI technology, and an easily adaptable interface, Docubee makes it easy to automate your most complex contracts and agreements.
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus and... -
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GPS to Radio-controlled Clock
GPS to Radio-controlled Clock
The purpose of this simple DIY project is to build an electronic circuit that received the GPS time signal, convert it to the radio-controlled clock format, and transmit that signal to the clock. Once built, there is no need for setup and maintenance, all you need is put this unit close to the window to receive GPS signal, and it will transmit the time signal to your radio-controlled clock. -
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ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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lpACLib
An Open-Source Library for Low-Power Approximate Computing Modules
The “lpACLib” library contains the VHDL description of accurate and approximate versions of several arithmetic modules (like adders and multiplier of different bit-widths) and accelerators. Moreover, it also provides the corresponding software behavioral models/implementations developed in C and MATLAB to enable quality characterization. Besides our novel designs, it also contains implementations for several state-of-the-art arithmetic modules and their approximate versions. This open-source... -
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ghdl-updates
GHDL - a VHDL simulator
GHDL is the leading open source VHDL simulator. *** Now on github.com/tgingold/ghdl *** We have binary distributions for Debian Linux, Mac OSX and Windows. On other systems, getting GHDL from here means downloading the current source package and building GHDL from source. Alternatively you can get the latest source version (warning : occasionally unstable!) by pulling a snapshot from the git repository. -
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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ApproxAdderLib
Library of Approximate Adders
... as hardware designers to evaluate their code and design. To the best of our knowledge, this is the first open-source library of approximate adders that facilitates reproducible comparisons and further research and development in this direction across various layers of design abstraction. This work is a result of collaborative effort between Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany and Vision Image and Signal Processing (VISpro) Lab at SEECS-NUST, Pakistan. -
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OpenSOC86
Open implementation of the x86 architecture
OpenSOC86 is an open implementation of the x86 architecture in Verilog. The current version only implements the 16-bit part (real mode). The processor is a pipelined architecture clocked at 100 MHz in a Cyclone II speed grade -6. Therefore it can be seen as similar to a 486 in real mode. Several peripherals are also implemented in a somewhat minimalistic way, but enough to be able to boot an IBM PCXT compatible bios and MSDOS 6.22. The current implementation is only proven to boot the bios... -
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Notepad++ Verilog Plugin
Verilog plugin for Notepad++
Verilog processor for Notepad++. Current features: - Instantiate a module - Insert registers/wires from a module - Generate a test bench template - Automatically inserts a default header for a test bench - Insert a clocked always block v1.2.0 now supports ANSI and non-ANSI module declarations. To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C. This selects the module and parses its components. After... -
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VHDL Notepad++ Plugin
VHDL Plugin for the Notepad++ Editor
VHDL plugin based on http://sourceforge.net/projects/nppvhdlplugin/ This version is enhanced to include: - Insert Instantiation - Insert Signals - Create Test Bench Framework - Insert Component - Make comments Doxygen compliant - Create New Behavioral/Structural Entity Template - Create New Package File Template - Insert Synchronous Process - Insert Asynchronous Process - Insert a Default Header The default header is set in the vhdlConfig.txt file. -
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libVerilogVPI
SEL for access verilog via PLI/VPI API. Tested with Icarus Verilog.
SFENCE Extension Library (SEL) for access verilog function via PLI/VPI API to calls of standard SFENCE Function_Function objects. -
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A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.
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NOCEXplore
Network-on-Chip design exploration tool based on SystemC.
NOCEXplore is a Network-on-Chip design exploration tool based on SystemC. It includes libraries and executables for easy and fast upgradeable NoC models and a set of shell scripts. The project started during the PhD of Stefano Gigli at DII of Universita' Politecnica delle Marche (http://www.dii.univpm.it/) under the supervision of Prof. Massimo Conti and contribution of several students. -
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openAut
Open Source Hardware For Industrial Automation
This project is aimed at producing open source hardware for real time use in industrial automation. This project will have a few sub-projects that will focus on individual hardware for various industrial purpose. Some of the sub-projects will be of type Field-IO Modules development, Analog-IO Module development etc.