Open Source VHDL/Verilog Scientific/Engineering Software - Page 3

OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.

Design and implementation of silicon and software for baseband processors conforming to IEEE wireless standards. Initial focus on WiMAX and WiFi.

A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.

Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)

Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned Features : Similar with mainstream market tools IDE and GUI Wrapper like : LabView©, Proteus©, MPLab©, Eagle CAD©, Tools Suite for Most Market Microcontroller. Tools suite for Arduino, Pinguino, Pic, AVR, ARM, Basic Stamp, Risc, other platform Fully Integrated IDE. Adobe PDF Help section SQL Connectivity Community Avail : https://www.facebook.com/Project-Core-2306-Nextgen-Eda-pcbradide-for-Mcumacoslinuxwindows-138250749681138/?fref=ts

Ray Tracing micro-processor RTMP. Features: * Programmable pixel shaders. * SIMD 32-bit ALU. * Hardware support for Octree scene traversal. * Ray intersection cache. * Support for mutiple instances of RTMP working concurrently.

Collection of VHDL libraries for ASIC/FGPA development

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.

VHDL that describes the digital circuits employed in a fiber Bragg grating interrogation system, currently implemented in a FPGA system.

Oscilloscope using a VGA monitor and a cpld

VSYML is an automated symbolic simulator for VHDL designs.

Tool-independent Makefile generator for VHDL models.

vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd

This project aims to generate video signal using an FPGA development board

Tool suite and libraries for developing system-c models. Tools for managing RTL projects.

The project uses the infrared camera from the wiimote to track hand gestures. This tracking is performed on an Altera DE2-70 FPGA

cccutils provide the sources of the CCC and the CCC-Fanout.

GIAnT (Generic Implementation ANalysis Toolkit) is a platform for physical analysis of (embedded) devices. Primarily designed for hardware security analyses, it is built around an FPGA-based board for fault injection and side-channel analysis. This project has been supported by the German Federal Ministry of Education and Research BMBF (grant 01IS10026A, Project EXSET).

xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.

The ixo.de USB JTAG pod and firmware allows to access JTAG-capable chips via USB and a protocol like Altera USB-Blaster.

SFENCE Extension Library (SEL) for access verilog function via PLI/VPI API to calls of standard SFENCE Function_Function objects.

m4-la is a Logic Analyzer written in VHDL for the Xilinx ML403 Development board featuring the Virtex4 FPGA. The user interface is written in C for Windows32 based platforms. Xilinx ISE and EDK tools compile the VHDL and MS Visual Studio compiles the UI.

This project is aimed at producing open source hardware for real time use in industrial automation. This project will have a few sub-projects that will focus on individual hardware for various industrial purpose. Some of the sub-projects will be of type Field-IO Modules development, Analog-IO Module development etc.

System on Chip design generator.