Search Results for "tree generator"

...This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents in the higher leve 5. removehierarchy : Verilog Hierarchy Removal Tool to ungroup all the instances in a given module 6. comparemoduleinterfaces - Diff module ports and parameter. Tool to compare the interfaces ( ports, parameters, SV interfaces ) between two versions of a Verilog module or two similar modules 7. Verilog Testbench Generator 8. VHDL Testbench Generator 9. Verilog Remove Assignments 10. Verilog Find Instances or Nets 11. Clock And Reset Tree Analyzer( Alpha)

AUDio MEasurement System - a multi-platfrom system for audio measurement through sound card in the PC. It contains: generator, oscilloscope, audio spectrum analyzer (FFT) and frequency sweep plot. Compiles and works under Linux, Windows and MacOS. Source code is available in "git" and as ZIP snapshot. For more information see README.md

Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.

A formal proof generator for the system of Fitch. Apart from Fitch diagrams it can also be used to generate truth tables or tree diagrams. Good support for hints and single-stepping. This program is used as the engine behind http://logica.ewi.tudelft.nl.