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...It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1.

ADopenPOWERLINK is an open source Ethernet Powerlink Controlled Node (Slave) solution using the Analog Devices ADSP-CM408F mixed signal processor (http://www.analog.com), along with Altera FPGA as network communication processor. The solution is based on openPOWERLINK provided by SYSTEC electronic (http://www.systec-electronic.com), B&R (http://www.br-automation.com) and Kalycito (http://www.kalycito.com). This release contains the necessary and required packages and documentation to setup the power-link controlled node using Analog Devices ADZS-CM408 EZLITE development board (http://www.analog.com/en/processors-dsp/cm4xx/adsp-cm408f/products/cm40x-ez/eb.html) as application processor, and a Terasic DE2-115 Altera FPGA development board as a communication processor.

This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.