Search Results for "file chip"

Integrated component-based and cellular automata (CA) Parallel DEVS simulator. Version: 8.0 [Aug `26], 7.0 [Jan `23], 6.1 [Apr. `21], 6 [Sep. `20] , 5 [Jul. `19], 4 [Mar. `18], 3 [Apr. `15], 2.1 [Feb. `09], 2 [`03] See PVM: Visual Persistent Hierarchical Component-based Modeler (https://acims.asu.edu/persistent-visual-modeler/ ) and CoSMoSim: hierarchical visual modeling, database model repository, families of models, statecharts, partial-code generation for XML/DEVS-Suite models...

The OARS app is a data logger developed to run on Android OS and devices containing an internal GPS ,along with micro-electro-mechanical systems (MEMS) chipset. Specifically the Invensence MPU-6000 or newer. This chip is a highly accurate inertial measurement unit, or (IMU). Contained within this small IMU is a 3-axis Accelerometer, 3-axis Gyro, and 3-axis Magnetometer. Along with a built in processor, it can calculate movements along 9-axis. Depending on platform and app setting, OARS can...

This package contains code for use with Short Read DNA Sequencing technologies, and includes packages for ChIP-Seq, Whole Transcriptome Shotgun Sequencing, Whole Genome Shotgun Sequencing, SNP Detection, Transcript expression and file conversion.

gpNoCsim++ is a Network-on-Chip simulator based on gpNoCsim that extends the gpNoCsim and adds new features such as: asynchroniztion (using multithreading), loading network traffic from file, new topologies(i.e WK-Recursive), GUI and reporting features.

neochip is a collection of algorithms for high-density oligonucleotide microarrays. The current version contains heuristic algorithms that attempt to improve the quality of arrays by re-designing their layout (the location of the probes on the chip).

The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.