Search Results for "java automation" - Page 5
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Showing 182 open source projects for "java automation"
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Verilog 2005 synthesizable subset parser built on ANTLR framework. 3-nov-2014: latest release here: https://github.com/gburdell/parser
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PPPP is a computer program used for partitioning parameterized orthogonal polygons into parameterized rectangles. With this program, it is possible to build rectangular corner stitching data structure for parameterized VLSI layouts.
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Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.
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Here is Archii (Automation and Remote Control for Home Intelligence and Interactivity). This french project proposes a set of Web Services dedicated to creation of a smarter house. It uses open-source products such as Petals ESB, FreeTTS...
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Keep company data safe with Chrome EnterpriseMake AI work your way with Chrome Enterprise. Block unapproved sites and set custom data controls that align with your company's policies.
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GOOD NEWS: The functionality provided by this utility is now part of Kicad itself. Well done Kicad team. Keep up the good work. ------ This utility takes an input DSN file, exported from Kicad for example, and enables the user to assign various thick
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ElectroMimic is an electronic circuit simulator in Java™. The simulator is focused on the piecewise-linear models normally used by undergraduate students, but can also be linked with external simulation software for more realistic results.
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In early stages of software process implantation, is hard to measure the company performance. So, this project aims to help this difficult by providing a measurement process tool for software factories continuos improvement program.
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This project is aimed to build an Open Source Manufacturing Execution System based on J2EE, JBoss technology. Intesity based optimization
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Cloud-based help desk software with ServoDeskWhat if You Could Automate 90% of Your Repetitive Tasks in Under 30 Days? At ServoDesk, we help businesses like yours automate operations with AI, allowing you to cut service times in half and increase productivity by 25% - without hiring more staff.
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Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported. Project branch continues to evolve: https://github.com/gburdell/nldb including addition of tclsh UI.
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The FBench is the ongoing development of an open-source graphical software tool for embedded automation components and systems based on the IEC 61499 standard. The project originates from the OOONEIDA Workbench pioneered by Dr. James Christensen in 2005.
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This is an attempt to build an Java GUI for a low cost digital storage oscilosope based on a RS232 interface.
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The VSR is a repository of tools and challenges in verification (see for example epubs.cclrc.ac.uk/work-details?w=33971). It is part of the international grand challenge on software verification (eg http://vstte.ethz.ch/pdfs/vstte-hoare-misra.pdf)
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SymtaP is a performance analysis tool to determine the worst case execution time for embedded real time applications.
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The SESAME (Simulation of Embedded System Architectures for Multilevel Exploration) software system is an embedded system co-simulation environment and research tool which implements the ideas of the SESAME project at the University of Amsterdam.
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Processes boolean functions which can be provided either as a list of 0s and 1s or which can be provided as a formula in first-order logic (using disjunctive or conjunctive normal forms). Internally the Quine McCluskey algorithm is used.
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Xcarecrows4MDA provides a complete toolset to build models and check their behavior for standalone applications or whole systems with a hierarchical, state driven approach. A test component checks the safety of the model under various situations.
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Java source to C source translator, which allows to write MCU programs in Java. Now AVR are supported, others can be added. Convenient Java methods instead of manual register handling.
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The aim of this project is to develop a GDSII viewer by using Java programming language. Efforts will be made especially on ease-of-use, efficiency, and capacity.
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HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
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Equivalence checking for two netlists of ORCAD schematic designs. Check out whether two netlists may generate the idendical PCB in later design stage, even if they are derived from different design procedures with different part-ref and siganl-name.
