Search Results for "chip"

CLOCK 3W is a library for Arduino that helps you interact with CLOCK 3W timekeeping module (made by FRIENDLY ELECTRONICS) or any other module based on DS1302 chip.

Still struggling with Excel to setup your pick and place machine ? Cad2Board reads component mounting information from Eagle, Altium Designer and Mentor Expedition PCB designs. Component or component groups can be assigned to feeder slots by drag and drop. Any modifications for PCB population can be defined to generate PCB variants, consider rotations from unusual tape and reel packaging or to account in advance for CAD library or PCB design bugs. Generated setup data is stored in a...

This R package can be used to identify TRMs using experimental evidence from a single ChIP-seq experiment. It combines computational predicted transcription factor (TF) binding sites, gene expression and protein-protein interaction (PPI) data and use it to predict TRMs.

Run-time libraries to support the Kitchen Sink, an all-purpose chemical process control board, based on the Atmel AVR ATmega1280 chip, using the Arduino core libraries.

ChIPOTle is a peak-finding algorithm used to analyze ChIP-chip microarray data

gpNoCsim++ is a Network-on-Chip simulator based on gpNoCsim that extends the gpNoCsim and adds new features such as: asynchroniztion (using multithreading), loading network traffic from file, new topologies(i.e WK-Recursive), GUI and reporting features.

HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.

ChIPOTle 2.0 is a user friendly tool for performing peak detection in ChIP-chip signal. The tool also has functions for probe sorting, signal normalization, replication merging, and multiple correction testing in a windows interface or *nix command line.

C Compiler for the Parallax Propeller Chip

The CHIP Cluster Generator attempts to create spatio-temporal cluster data in an automated fashion to help evaluate epidemic detection software. The spatio-temporal data will then be used to determine robustness of spatial detection algorithms.

neochip is a collection of algorithms for high-density oligonucleotide microarrays. The current version contains heuristic algorithms that attempt to improve the quality of arrays by re-designing their layout (the location of the probes on the chip).

The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.

Chip programming software to support any programming hardware and devices to program. New chips and new programming hardware support to be added via DLL. Automagic check on whether hardware can program chip.

This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.

...It is written in PHP and currently uses SQLite 2.1, but could be converted to MySQL. It was partially developed with a working micro lab. Looking for some people to chip in and make it a nice project.