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Simple tool for drawing Finite State Machines (FSMs).
StateS has moved to GitHub and will no longer be updated on SourceForge.
New link: https://github.com/ClementFoucher/StateS
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
This project is ported to github and can be found at:
https://github.com/chiphackers/covered
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Automata Based Programming Tool for implementing logic for J2SE, J2EE and Sybmian applications. Consists of Java FSM Framework and Eclipse Plugin parts. Plugin implements UML model editor, visual debugger, validator, compiler and interpreter for Eclipse
jFAST is a simple finite automata (FA) graphical simulation utility; it is designed to feature simple mechanisms for creating, editing, and simulating FA. jFAST is ideal for use by students, instructors, and self-guided explorers alike.
This is a generalized version of the famous Langton Ant, which is a FSM (Finite State Machine) with two states. This little program give you the change to describe a FSM with up to eigth states.
This library is an implementation of an extensible dynamic configurable finite state machine (FSM). The configuration of the state machine is not compiled, but loaded at the runtime from a file or created by application.