Search Results for "risc"
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Showing 3 open source projects for "risc"
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Mecrisp - A family of optimising native code Forth implementations for MSP430, ARM Cortex M, RISC-V RV32IM(C), MIPS M4K and FPGAs.
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QUASI is stand-alone AVR RISC processor simulator with debugging features, EDA-like GUI and plugin interface.
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This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.
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