Search Results for "simulator processor"
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Showing 29 open source projects for "simulator processor"
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PicoBlaze_Simulator_in_JS
A simulator of Xilinx PicoBlaze soft-processor, runnable in browsers.
A web-based assembler for and emulator of Xilinx PicoBlaze. -
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simdop
Application for simulation of microprogrammed processor DOP
...With this simulator you can simulate one clock or large amount of microinstructions of DOP processor. It's easy and user-friendly. -
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Uruk GNU/Linux
Uruk GNU/Linux fast, simple and strength GNU/Linux distribution
Uruk GNU/Linux is a distribution of the GNU operating system, with the Linux-libre kernel. It comes ready for home and office use, and programs are easy to find and install. In this time Uruk GNU/Linux is based on PureOs core. Uruk GNU/Linux use "Mate DE" as a default desktop -
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FastSim consists of: - 'Facile' a highly flexible and expressive processor-architecture specification-language. - A compiler for the specifications which produces high-performance, fast-forwarding simulators.
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simutron
AVR simulator IDE
Electronic circuit simulator. Simple environment to run and debug firmware for AVR 8-bit microprocessors. Able to run arduino firmware. Internally this program uses the open source Simavr AVR Processor Simulator (https://github.com/buserror/simavr) and wraps all its functions in a GUI shell. Setups for firmware debugging scenarios can be created dynamically. -
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dps8m
A simulator for the Multics dps-8/m mainframe
...2015-11-05: The Ritter Park RCC Multics installation was "[T]aken down after a month of uptime." 2017-03-07: The DPS8M Development Team released Multics Release MR12.6f. 2017-07-08: Announcing v1.0 The purpose of this project is to create a simulator reproducing in sufficient detail the function and capabilities of the Honeywell/Bull dps-8/m processor with the ultimate goal of resurrecting Multi -
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or1ksim64KPU
Krypto-processor (KPU) on OpenRISC architecture
This simulation of a KPU (general purpose Krypto-processor) extends the OpenRISC or1ksim simulator to cover the OR 64-bit standard, and runs encrypted in user mode with 32-bit data and addressing encrypted in 64 bits of physical space. Privileged supervisor processes cannot read user-mode data, nor modify it without being noticed. This demonstration shows that it is possible to modify standard architectures (such as OR) to support KPU operation. -
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SimuS
A didatic processor simulator
This is an integrated IDE, consisting of an editor, an assembler and a simulator for an 8-bit didatic processor named Sapiens. It is intended for educational purposes. It is written in Object Pascal, and fully compatible with Lazarus framework. You can find the sources for the version compatible with Raspberry Pi at https://github.com/sottam/simus. Check our new book: https://goo.gl/cSH6rU -
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DigMIPS
A simple MIPS processor for Chipmunk DigLog circuit simulator
- DigMIPS is a simple 1-cycle-per-instruction MIPS processor working under DigLog circuit simulator. - DigMIPS is provided with an assembler and a C compiler. - DigMIPS serve as a nice support to teach the basics of computer architecture. Features: - 8 instructions - 8K RAM + 8K ROM - I/O periphals (keyboard and teletype screen) Software: - DigASM (assembler) - DigCC (C compiler) -
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SkyEye
a very fast full system simulator
SkyEye is a very fast full system simulator which takes llvm as IR of dynmic compiled framework.. It can simulate series ARM, Coldfire,Mips, Powerpc, Sparc, x86, TI DSP and Blackfin DSP Processor. Also can simulate multicore system by the multicore of host. The commercial support is provided by DigiProto Co. (http://www.digiproto.com) -
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openDLX
A DLX/MIPS processor simulator
openDLX is a DLX/MIPS ISA compatible pipeline simulator. (Visit https://github.com/smetzlaff/openDLX for the latest development version or if You want to contribute.) -
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ParallelSim
ParallelSim is a parallel processor simulator written in java.
ParallelSim is a parallel processor simulator written in Java which shows the effect of increasing the workload keeping the number of processing elements constant in one simulation. The number of processors is scalable and can be increased in subsequent iterations of simulation. The parameters like initial load, load offset, number of processors are declared as constants and can be changed directly in the source code to emulate different scenarios. -
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SCHEDuler SIMULAtor (originally sched_sim) is a simple C++ event driven simulator of scheduling policies (single processor). Currently supported scheduling policies are: FIFO, LIFO, EDF, LST, RM, DM.
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DASiT
DASiT (DLX-Altivec Simulator Tool)
DASiT is a simulation teaching tool based on DLX processor that includes multimedia set-instructions by incorporating AltiVec SIMD extensions. The tool developed in Java displays DLX pipeline execution with its data path that incorporates visualization of memory and register. It is considered as a complement in undergraduate computer design and computer architecture subjects. -
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Processor and realtime viewer for the program VXFlow (http://www.morgenthal.org/vxflow/), an numerical flow field simulator, written by Prof. Dr. Guido Morgenthal (http://www.uni-weimar.de/Bauing/MSK/?lang=en). This project uses the gloost framework.
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A graphical simulator for the LC3 processor, concentrating on the micro-architecture level. The processor is thoroughly described in "Introduction to Computing Systems: From Bits & Gates to C & Beyond" by Yale Patt and Sanjay Patel (ISBN-0-07-246750-9
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JPACS, Java Processor and Cache Simulator, was developed to give a simple and clear tool to simulate a processor with a complete associative memory cache at ISA level, using direct memory access or using a program written in assembly.
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A simulator of Donald E. Knuth's fictitious MIX processor written in Java, which includes support for floating-point arithmetics.
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Tori assim is an assembler for the educational Txori assembly language and simulator for the bird processor. It's being developed as an open source clone for the closed source and windows only BIRD.
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DSPemu emule a digital signal processor TMS320F243, with console interface showing the registers and memory. With DSPemu is possible test algorithms such as Filter, FFT/IFFT. This can be integrate and used with a circuit simulator.
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This project provides a tool-chain for compiling C code for the SPEAR2 processor. It comprises a C compiler (GCC), an assembler/linker, a macro assembler, a basic library and a simulator.
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QUASI is stand-alone AVR RISC processor simulator with debugging features, EDA-like GUI and plugin interface.
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Superscalar processor simulator for in-order and out-of-order processors. It also simulates several configurations of multiprocessors. Currently only supports the MIPS instructions set.
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Gnu Digital Signal Processor Simulator. The goal is to develop a DSP Simulator for Linux. The first chip supported will be the TMS320C54x.
