Search Results for "risc" - Page 2
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Showing 76 open source projects for "risc"
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Find Hidden Risks in Windows Task SchedulerWindows Task Scheduler might be hiding critical failures. Download the free JAMS diagnostic tool to uncover problems before they impact production—get a color-coded risk report with clear remediation steps in minutes.
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OpenMandriva Lx
Easy, yet powerful, GNU/Linux distribution
OpenMandriva Lx is a unique and independent distribution and direct descendant of Mandriva Linux. It comes from a 100% community-driven association that believes in the values of free software & collaboration and whose founding values are development, equality, co-operation, openness, freedom, group achievement, independence, and solidarity. Source code: Software: https://github.com/OpenMandrivaSoftware Packages: https://github.com/OpenMandrivaAssociation Build... -
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amforth: Interpreter on Microcontrollers
amforth is an extendible interpreter on microcontrollers
amforth is an extendable command interpreter running on AVR ATmega and TI MSP430 microcontrollers. The Risc-V and ARM architectures are ascending. Turnkey actions for IoT workloads are possible as well. The command language is close to the Forth 2012 standard. -
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UniSIMD-assembler
SIMD macro assembler unified for ARM, MIPS, PPC and x86
UniSIMD assembler is a high-level C/C++ macro assembler framework unified across ARM, MIPS, POWER and x86 architectures. It establishes a subset of both BASE and SIMD instruction sets with clearly defined common API, so that application logic can be written and maintained in one place without code replication. The assembler itself isn't a separate tool, but rather a collection of C/C++ header files, which applications need to include directly in order to use. At present, Intel... -
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A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.
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CrossBrowdy
JavaScript framework to build game engines, games, emulators and apps
CrossBrowdy is a free and open-source JavaScript framework that allows to create multimedia apps, emulators, game engines and games that will be compatible with any device. Any software developed with CrossBrowdy should be able to be used in any JavaScript compatible web client (including browser plug-in, add-on, extension, app...) which supports "document.getElementById". This framework allows any developer to manage easier many different things, such as audio (with Flash fallback,... -
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OmniEdge
Bringing intranet on the internet with Zero-Config Mesh VPNS.
OmniEdge is an Open source p2p layer 2 , zero-config mesh VPN infrastructure, a traditional VPN, AWS VPC, Ngrok, DDNS alternative. No central server, easy to scale with less maintenance. What happens in intranet, stays in in intranet. -
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RARS
RISC-V Assembler and Runtime Simulator
RARS, the RISC-V Assembler, Simulator, and Runtime, will assemble and simulate the execution of RISC-V assembly language programs. Its primary goal is to be an effective development environment for people getting started with RISC-V. -
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Selfie
An educational software system of a tiny self-compiling C compiler
An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosting RISC-V hypervisor. Selfie is a project of the Computational Systems Group at the Department of Computer Sciences of the University of Salzburg in Austria. The Selfie Project provides an educational platform for teaching undergraduate and graduate students the design and implementation of programming languages and runtime systems. -
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Rocket Chip
Rocket Chip Generator
Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. A diplomacy framework (LazyModules) lets designers wire components with negotiated parameters, enabling reuse and rapid exploration of different cache sizes, port counts, and memory hierarchies. ... -
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WINIX OS
A UNIX-style Operating System for the Waikato RISC Architecture
Winix is an experimental Unix-like operating system kernel written in modern C++ with an emphasis on object-oriented design and code clarity. It is a pedagogical project exploring how kernel-level programming can be structured with C++ abstractions while maintaining low-level control. Winix supports basic system services such as file systems, process management, and a terminal interface, and is designed for booting on x86_64 hardware via QEMU. It serves as an accessible and unconventional... -
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rCore-Tutorial-v3
Let's write an OS which can run on RISC-V in Rust from scratch
rCore-Tutorial-v3 is an educational project designed to guide learners through the process of building a minimalistic operating system from scratch using the Rust programming language. Targeting the RISC-V architecture, this tutorial emphasizes safety and concurrency, leveraging Rust's features to teach OS fundamentals such as memory management, process scheduling, and file systems. It is structured to provide hands-on experience, making it suitable for both academic settings and self-study. -
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Bareflank Hypervisor
lightweight hypervisor SDK written in C++
The Bareflank Hypervisor is an open source hypervisor Software Development Toolkit (SDK) for Rust and C++, led by Assured Information Security, Inc. (AIS), that provides the tools needed to rapidly prototype and create your own hypervisor on 64bit versions of Intel and AMD (ARMv8 CPUs, RISC-V and PowerPC also planned). The Bareflank SDK is intended for instructional/research purposes as it only provides enough virtualization support to start/stop a hypervisor. Bareflank can also be used as the foundation to create your own, fully functional hypervisor as it uses the MIT license, and includes 100% unit test coverage and compliance for AUTOSAR. ... -
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TensorBase
TensorBase is a new big data warehousing with modern efforts
TensorBase hopes the open source not become a copy game. TensorBase has a clear-cut opposition to fork communities, repeat wheels, or hack traffic for so-called reputations (like Github stars). After thoughts, we decided to temporarily leave the general data warehousing field. For people who want to learn how a database system can be built up, or how to apply modern Rust to the high-performance field, or embed a lightweight data analysis system into your own big one. You can still try, ask... -
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The RISC OS Search Engine is a python-based search engine that spiders around the Internet searching specifically for software which runs on RISC OS. It features three processes - a Watchdog process, a Spidering process and a Web UI process. It required Python 3.6 - 3.9, CherryPy and MongoDB. Although specifically for RISC OS, it will currently only run on Windows and UNIX.
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RISC-V BOOM
SonicBOOM: The Berkeley Out-of-Order Machine
The riscv-boom project (also called BOOM or SonicBOOM) implements a high-performance, synthesizable out-of-order RISC-V core written in the Chisel hardware construction language. It targets the RV64GC (i.e. 64-bit with general + compressed + floating point) instruction set and supports features such as virtual memory, caches, atomics, and IEEE-754 floating point. The design is parameterizable, meaning users can tune pipeline widths, buffer sizes, functional units, and other microarchitectural knobs to explore tradeoffs. ... -
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Pharos
RTOS for Secure, Safe and Real-Time Systems
Pharos is a free open-source RTOS for secure, safe and real-time systems with the following characteristics: - Memory and enhanced time partitioning (TSP) - Native support for sporadic, periodic and aperiodic threads - Fixed-priority preemptive scheduler - Execution time protection (threads are prevented from executing for more time than they are configured to) - Small size (full image has ~100 to 300KiB text, ~30KiB data) - Hard real-time determinism - Fast critical sections - Prioritized nested interrupts - inter-partition communication with filters to protect unwanted access - Multicore support (RMP) - Supports ARM9, Cortex-A/R/M and Aarch64, RISC-V64 (64 bits) - The complete TestSuite (see below information) is run successfully for each platform in each release - Tested: more than 170 KLOC of requirement-based tests, executed for each board at each release - Up-to-date User Manual also available See our wiki page for more information. -
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jMIPS
MIPS processor in Java
A MIPS processor modeled in Java for educational purposes and aimed at undergraduate Computer Architecture courses. It presently runs MIPS 32-bit R3000 ELF executables on any platform where Java itself will run. Five successively more sophisticated models of a pipelined MIPS RISC processor are included. Though the code is deliberately kept clear and simple in order that readers are able to figure out how a real processor works through the medium of the code, it will soon be able to run a real Linux O/S kernel compiled for MIPS in Java - at what speed we don't know! -
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Project 2306 IDE Rad MacOS MCU DeveR
Electronic design and programming tools suite like Eagle, MpLab
...All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned Features : Similar with mainstream market tools IDE and GUI Wrapper like : LabView©, Proteus©, MPLab©, Eagle CAD©, Tools Suite for Most Market Microcontroller. Tools suite for Arduino, Pinguino, Pic, AVR, ARM, Basic Stamp, Risc, other platform Fully Integrated IDE. Adobe PDF Help section SQL Connectivity Community Avail : https://www.facebook.com/Project-Core-2306-Nextgen-Eda-pcbradide-for-Mcumacoslinuxwindows-138250749681138/?fref=ts -
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RexSimulator
A full simulator of the WRAMP CPU and REX board.
This project is a simulator of the WRAMP (Waikato RISC Architecture MicroProcessor) CPU used at the University of Waikato for teaching computer architecture concepts, along with the Rex board that contains the CPU. -
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tisift
imap cleanup & command line tool
...Example: # Set MsgId on Mails without one FOLDER="Archives" ; tils -I "$FOLDER" |grep "\{"|while read LINE ; do tish -x addheader "$FOLDER" "$LINE" "X-New-Header: true" ; done # Correct Date to second received header: tish date Archives PATTERN received2 # Import or export mbox tish exportmbox Archives >file.mbox tish importmbox Archives <file.mbox Written in ruby. Attention: Use on your own risc! You can damage your whole mail data! -
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32-BIT GENERAL PURPOSE INTEGER PROCESSOR
Simple single cycle processor based on triadic Harvard architecture.
A 32-bit MIPS simple single cycle processor based on triadic Harvard architecture with a RISC-like ISA. This project is done in Cairo University-Faculty of Enigneering, Electronics and Electrical Communication department (EECE-2017) -
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aun-filestore
Econet Fileserver (using AUN)
aun-filestore is a Econet Fileserver implementation (using AUN) for Linux and other platforms. It's written in PHP, provides file and print services to Acorn Risc Machines, and Emulated BBCs. The project is now at the beta stage, and works well for BBC clients. It handles all file operations however print operations now work with all print jobs being spooled to disc. A basic text file auth backend is done working, however all filestore users access the unix fs as the user the filestore runs as. ... -
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Brandy Basic V Interpreter
Brandy is an interpreter for BBC Basic
Brandy is an interpreter for BBC Basic (or Basic V) that runs under a variety of operating systems. Basic V is the version of Basic supplied with desktop computers running RISC OS. These were originally made by Acorn Computers.
