Search Results for "risc"
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Showing 8 open source projects for "risc"
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Mecrisp - A family of optimising native code Forth implementations for MSP430, ARM Cortex M, RISC-V RV32IM(C), MIPS M4K and FPGAs.
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CRC RevEng
Arbitrary-precision CRC calculator and algorithm finder
CRC RevEng is a portable, arbitrary-precision CRC calculator and algorithm finder. It calculates CRCs using any of the 113 preset algorithms, or a user-specified algorithm to any width. It calculates reversed CRCs to give the bit pattern that produces a desired forward CRC. CRC RevEng also reverse-engineers any CRC algorithm from sufficient correctly formatted message-CRC pairs and optional known parameters. It comprises powerful input interpretation options. Compliant with Ross Williams'... -
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Project 2306 IDE Rad MacOS MCU DeveR
Electronic design and programming tools suite like Eagle, MpLab
...All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned Features : Similar with mainstream market tools IDE and GUI Wrapper like : LabView©, Proteus©, MPLab©, Eagle CAD©, Tools Suite for Most Market Microcontroller. Tools suite for Arduino, Pinguino, Pic, AVR, ARM, Basic Stamp, Risc, other platform Fully Integrated IDE. Adobe PDF Help section SQL Connectivity Community Avail : https://www.facebook.com/Project-Core-2306-Nextgen-Eda-pcbradide-for-Mcumacoslinuxwindows-138250749681138/?fref=ts -
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Brandy Basic V Interpreter
Brandy is an interpreter for BBC Basic
Brandy is an interpreter for BBC Basic (or Basic V) that runs under a variety of operating systems. Basic V is the version of Basic supplied with desktop computers running RISC OS. These were originally made by Acorn Computers. -
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QUASI is stand-alone AVR RISC processor simulator with debugging features, EDA-like GUI and plugin interface.
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This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.
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Virtual machine/emulator; "holding pen" for self-replicating programs written in custom RISC assembly-like language, evolving via random point mutations and periodic fitness-based cullings. Inspired (like Avida) by Thomas Ray's alife simulator, Tierra
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Distributed Genetic Programming SRVM (Simple Risc Virtual Machine) Distributed function approximator of nonlinear functions with automatic induction of machine code.
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