Showing 4 open source projects for "threads g-code generator"

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  • 1
    Open Source Cartridge Reader

    Open Source Cartridge Reader

    A shield for the Arduino Mega that can back up video game cartridges

    ...Supported cartridge types so far, LoRom, HiRom, ExHiRom, DSP, SuperFX, SuperFX2, SDD1, CX4, SPC7110, SA1 (last two chips need Adafruit Clock Generator). Reads and writes SNES Satellaview 8M Memory packs (BS-X cartridge and Adafruit Clock Generator needed). Reads and writes Nintendo Power Super Famicom Memory Flash Cartridges (needs Adafruit Clock Generator for best result).
    Downloads: 2 This Week
    Last Update:
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  • 2

    COBOL copybook to XML converter

    Converts cobol copybooks to Xml/Java objects

    CB2XML (CopyBook to XML) is a COBOL CopyBook to XML converter written in Java and based on the SableCC parser generator. This project includes utilities to convert an XML instance file into its COBOL copybook equivalent string buffer and vice versa. Source is now available in GitHub: https://github.com/bmTas/cb2xml
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    Downloads: 2 This Week
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  • 3
    Open source Algol 68 implementations

    Open source Algol 68 implementations

    Implementations for the Revised Report language

    ...The project offers two implementations: Implementation 1 is Algol68G: a recent checkout hybrid compiler/interpreter by Marcel van der Veer, supporting arbitrary arithmetic, partial parametrisation, complex numbers, POSIX threads, GNU plotutils, GNU scientific library, curses, sound, TCP sockets, RegEx and PostgreSQL. Inplementation 2 is algol68toc, a port by Sian Mountbatten of the vintage Algol68RS (UK Defense Research Agency) compiler. The implementation emits C code.
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    Downloads: 4 This Week
    Last Update:
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  • 4

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 0 This Week
    Last Update:
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