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Showing 2 open source projects for "cpu chip"

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    This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.
    Downloads: 0 This Week
    Last Update:
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  • 2
    Yet Another DLX based Architecture System On a Chip (YADASOC) is a RTL Verilog implenetation of a DLX based CPU and subsystems.
    Downloads: 0 This Week
    Last Update:
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