Search Results for "command line dynamic"
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14 projects for "command line dynamic" with 2 filters applied:
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Ship Agents FasterGemini Enterprise Agent Platform lets you rapidly build, scale, govern and optimize production-ready agents grounded in your organization's data. The platform enables developers to build custom or pre-built agents for virtually any use case. New customers get $300 in free credits.
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MongoDB Atlas runs apps anywhereMongoDB Atlas gives you the freedom to build and run modern applications anywhere—across AWS, Azure, and Google Cloud. With global availability in over 115 regions, Atlas lets you deploy close to your users, meet compliance needs, and scale with confidence across any geography.
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S.M.A.R.T. Monitoring Tools
Disk Inspection and Monitoring
smartmontools contains utility programs (smartctl, smartd) to control/monitor storage systems using the Self-Monitoring, Analysis and Reporting Technology System (S.M.A.R.T.) built into most modern ATA and SCSI disks. It is derived from smartsuite. -
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GlobalPlatform
Implementation of GlobalPlatform smart card specification
The GlobalPlatform card specification is a standard for the management of the contents on a smart card. Mainly this comprises the installation and the removal of applications. This project offers a C library and a command line shell. Find more information on https://kaoh.github.io/globalplatform/ -
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NB: Development has been moved to Github: https://github.com/avrdudes/avarice AVaRICE is a program for interfacing the Atmel JTAG ICE to GDB to allow users to debug their embedded AVR target.
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
Earn up to 16% annual interest with Nexo.Generate interest, access liquidity without selling, and execute trades seamlessly. All in one platform. Geographic restrictions, eligibility, and terms apply.
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owfs and owhttpd
Project moved to https://github.com/owfs/owfs/
Please note that OWFS source code, and all Issue/Tickets/merge requests have now been moved to https://github.com/owfs/owfs/. Developer mailing lists will still be kept at Sourceforge. ---- OWFS -- 1-Wire file system. Use the Dallas 1-Wire and iButton chips with standard filesystem commands. Create temperature loggers. Monitor everything. OWHTTPD -- same system, only used as a light weight web server. OWFS is also ported to embedded routers, Mac OSX and Windows. Basically you can use... -
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rkflashtool
Tools for flashing Rockchip devices
Tools for flashing Rockchip devices. -
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Windows User Space AppleSMC Driver
Windows User Space AppleSMC Driver (64-bit only)
A Windows User Space AppleSMC Driver based on InpOutx64 and applesmc.c Linux kernel driver -
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Geforce Driver Check (GDC)
Nvidia Display Driver auto installer and version checker
Checks for new Nvidia Geforce Display Drivers then does an automated unattended install, or with many more options. You can silent install, and only just install the basics, no bloat! Instantly check to see if you have latest driver offering. -
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DAISHO is a Bash Script to Automate MACCHANGER. Daisho Is Designed to work on Unix systems like Ubuntu, Fedora, Back-Track, Red-HAT.
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Save Up to 91% on Cloud Compute With Spot VMsRun batch jobs at 60-91% off with Spot VMs. Long-running workloads get automatic discounts with sustained use.
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Download GPS track from the GPS logger "Solmeta Geotagger Pro" under Linux; Auslesen des Geotaggers * Geotag images with image direction, pitch, roll; Geotagging mit Blickrichtung * Altitudes/Höhen from geonames.org * NMEA analysis: DOP, satellite
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FPGAsm
Create fast bare-metal FPGA designs without Verilog or VHDL
FPGAsm is a low-level alternative to verilog and VHDL. A near-instant 'assembler for FPGAs', this simple yet powerful language facilitates bottom-up design, layout and wiring of modules, and generation of .xdl output. With about 10 keywords to learn, you can start making circuits in minutes. Now you can focus on learning the ins and outs of the FPGA instead of complex tools and languages. Fast turnaround time and bottom-up approach invite exploration, experimentation, live circuit... -
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