Search Results for "set"

A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.

...This project proposes a FID driver that exposes Spectranet's extra memory as a ramdisk to the CP/M Plus system. Changes in v1.1: keep floppy drive motor state (as set by CP/M) when paging in Spectranet RAM (to avoid motor jumps). Unfortunately, motor state is controlled by the same hardware register as +3's memory paging features! Changes in v1.2: Avoid using Spectranet RAM page 0 used by the device itself. Thanks to this change this driver can be used with the upcoming driver for networked disk image. ...

...The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic registers.

...This project is the early development stage. All help is appreciated. Purpose: Create a generic packet driver for DOS to work on the RT8101 RTL8136 and RTL8139 chip-set.

The Wolfram Machine project is an effort to create a set of documentation and useful modules (both hardware and software) for a computing architecture based on the mathematical theories presented in Steven Wolfram's book _A_New_Kind_of_Science_.

Maiden-core is a Linux kernel robotics API module, extensible in Erc. The Maiden Project also documents and develops the Maiden architecture for mobile robots, a set of (optional) designs and standards for robots using the Maiden-core API.

This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.