Search Results for "risc-none-embed-gcc"
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Showing 5 open source projects for "risc-none-embed-gcc"
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A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.
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cMIPS
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips The code here is no longer up to date. The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5%... -
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A lightweight, simple and easy to use embedded system task scheduler. RataOS is written as a high level C, with a simple HAL & API structure, allowing it to be ported between embedded devices easily.
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This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.
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We are currently developing our embedded TCP/IP modules, industrial ethernet systems and wireless platform for system control and data acquisition. Our main development environment is Linux and GNU tools like GCC (ASM, C, C++) and Python.
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