Search Results for "state machine editor"
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Showing 5 open source projects for "state machine editor"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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Interrupt-Driven Software UART
Interrupt Driven Software UART based on Atmel Software Framework
Interrupt-Driven Software UART based on Atmel Software Framework , tested on SAM3 Cortex M3 at 57600bps Start bit detection is managed by programmed GPIO falling edge interrupt handler, For bit timing is used timer counter, compare interrupt handler. Timer handler raises every 0.5 bit time periode and data sampling is managed by state machine in timer handler subroutine. Software can be used for any pin which supports external interrupt. -
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Cobos Project
the disruptive IDE for COBOL developers
The Cobos Project is an Open Source initiative from Metrixware, dedicated to Mainframe COBOL CICS, DB2, IMS developments within the Eclipse Platform. -
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RHexLib is the control software library for the RHex robot (see http://ai.eecs.umich.edu/RHex for more information). It features an efficient real-time static scheduler, low level motion control tools, state machine based controller designs and various
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MachDB is machine database to catalog of the changing state of your hosts. It consists of a database, an aggregator, an XML spec and some example information gathering scripts. Along with a Web UI, these form the basis of a system that will allow you to
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