Search Results for "qualnet simulator software"

EduMIPS64 (aka edumips) is a cross-platform MIPS 64 ISA simulator. It can be used to run and debug MIPS programs that are written using the MIPS64 instruction set. It supports visual debugging and lets you see what instructions do in the pipeline.

This is a small library that allows comunicating with a Webasto (tm) W-Bus capable car heating system. Runs on Personal Computers or for embedded devices (slim design). Easily portable. Includes a Heater manager, heater controller program and more. The GIT repository (CVS is deprecated) also includes a control unit application to control W-Bus capable devices, a W-Bus compatible heater unit firmware application and a heater simulator for testing purposes. Also, a serial port loop back...

This project intends to modelize a framework for remote controlled airplanes. This framework includes PPM/PCM drivers and data telemetry (location, speed, altitude) based on the SensorsAPI, to provide a reliable augmented reality for FPV flights

Development of software emulator for BESM-6, old soviet mainframe. This project has been split and moved to: https://github.com/besm6/simh - BESM-6 simulator https://github.com/besm6/dispak - DISPAK simulator https://github.com/besm6/besm6-archive - disk images https://besm6.github.io/ - examples, DISPAK sources and KRAB sources

VisualVNC is a connector between virtual network and physical network. A virtual network mainly refers to the topology created by GNS3 (Graphical Network Simulator, a popular network simulator), the physical network means the real machines or virtual machines (created by VMware, virtualbox and so on) which are running Windows.

...Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)

This is a simulation of an open CPU, called 67-80-85. It tries to implement a simple, efficient CPU. It includes the simulator, an assembler, a sample code for a boot loader (ROM), a microkernel prototype and tests. - "The 3-legged shinning steel horse

This project is about the graphical simulation of pipelining mechanism in Central Processor Unit. It includes (1) INES Components package created in Delphi, which allows fast building of simple simulators; (2) INES - simulator created with this package.

FlightGear Controller (fgctrl) is a combination of software and hardware (mostly AVR-based) that let you build a simplified cockpit for controlling aircraft in FlightGear and other flight simulators.