Search Results for "pipeline simulator"
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Showing 7 open source projects for "pipeline simulator"
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StereoKit
An easy-to-use mixed reality library for building VR applications
StereoKit is an easy-to-use open source mixed reality library for building HoloLens and VR applications with C# and OpenXR! Inspired by libraries like XNA and Processing, StereoKit is meant to be fun to use and easy to develop with, yet still quite capable of creating professional and business-ready software. HoloLens 2, Oculus Quest, Windows Mixed Reality, Oculus Desktop, SteamVR, Monado (Linux), and eventually everywhere OpenXR is! Flat screen MR simulator with input emulation for easy... -
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EduMIPS64 (aka edumips) is a cross-platform MIPS 64 ISA simulator. It can be used to run and debug MIPS programs that are written using the MIPS64 instruction set. It supports visual debugging and lets you see what instructions do in the pipeline.
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gem5-STNoC
Cycle-approximate STNoC instance in gem5
The gem5-STNoC model available here (https://sourceforge.net/projects/gem5-stnoc) in alpha version is adapted from the gem5 Garnet Fixed Pipeline as a cycle-approximate NoC model based on STMicroelectronics STNoC backbone specifications. It supports several mechanisms implemented at the STNoC Network Interface, such as NoC Firewall and preliminary Memory Interleaving. The model is freeware covered by standard gem5 license. Development has been partly supported by EU-ICT projects DREAMS... -
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openDLX
A DLX/MIPS processor simulator
openDLX is a DLX/MIPS ISA compatible pipeline simulator. (Visit https://github.com/smetzlaff/openDLX for the latest development version or if You want to contribute.) -
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DASiT
DASiT (DLX-Altivec Simulator Tool)
DASiT is a simulation teaching tool based on DLX processor that includes multimedia set-instructions by incorporating AltiVec SIMD extensions. The tool developed in Java displays DLX pipeline execution with its data path that incorporates visualization of memory and register. It is considered as a complement in undergraduate computer design and computer architecture subjects. -
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YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.
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