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Full-stack observability with actually useful AI | Grafana Cloud
Our generous forever free tier includes the full platform, including the AI Assistant, for 3 users with 10k metrics, 50GB logs, and 50GB traces.
Built on open standards like Prometheus and OpenTelemetry, Grafana Cloud includes Kubernetes Monitoring, Application Observability, Incident Response, plus the AI-powered Grafana Assistant. Get started with our generous free tier today.
myFocuserPro2 (myFP2) is an ASCOM - INDI - LINUX - WINDOWS telescope focuser with a large range of options.
315,000+ file downloads. The most popular focuser project.
(c) Copyright Robert Brown 2014-2025. All Rights Reserved.
Code or portions of code may not be copied or used without written permission from the author.
Other Focuser Projects
myFP2ESP32 WiFi - https://sourceforge.net/projects/myfocuserpro2-esp32/ [ESP32 Only]
myFP2ESP8266 WiFi -
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An ESP32-Dev WiFi focuser. DIY or PCB designs.
(c) Robert Brown 2014-2025, Holger M, 2019-2021. All rights reserved.
Code or portions of code may not be copied or used without appropriate credit given to authors.
Spreadsheet to calculate what stepper motor to use.
https://sourceforge.net/projects/arduinoascomfocuserpro2diy/files/Documentation/Nema-Stepper-Motors.xlsx/download
Spreadsheets to calculate...
MisterHouse is a Windows/Unix home automation program written in Perl. It can respond to voice commands, web browsers, time of day, serial port and X10 data, external files, etc and can speak via Text to Speech engines.
Support is on https://sourceforge.net/p/misterhouse/mailman/misterhouse-users/ and code is maintained on https://github.com/hollie/misterhouse
CPU Hot Plugging (chp) is created by Kafabih (kr code) inspired by Thunderzap android custom kernel cpu governor to reduce battery consumptions because of your laptop CPU usages.
Please use carefully, chp can cause system crash or hang because of hot plugging cpu core.
This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.