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  • 1
    vMAGIC
    vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
    Downloads: 0 This Week
    Last Update:
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  • 2
    The PARSEC CEE is the primary achievement of several years of effort at NASA's Marshall Space Flight Center. The CEE was developed to allow engineers in the Advanced Concepts Department to rapidly prototype launch vehicle and spacecraft concepts.
    Downloads: 1 This Week
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  • 3
    Verilog 2005 synthesizable subset parser built on ANTLR framework. 3-nov-2014: latest release here: https://github.com/gburdell/parser
    Downloads: 0 This Week
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  • 4
    PPPP is a computer program used for partitioning parameterized orthogonal polygons into parameterized rectangles. With this program, it is possible to build rectangular corner stitching data structure for parameterized VLSI layouts.
    Downloads: 0 This Week
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  • 5
    Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.
    Downloads: 0 This Week
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  • 6
    GOOD NEWS: The functionality provided by this utility is now part of Kicad itself. Well done Kicad team. Keep up the good work. ------ This utility takes an input DSN file, exported from Kicad for example, and enables the user to assign various thick
    Downloads: 0 This Week
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  • 7
    ElectroMimic is an electronic circuit simulator in Java™. The simulator is focused on the piecewise-linear models normally used by undergraduate students, but can also be linked with external simulation software for more realistic results.
    Downloads: 0 This Week
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  • 8
    This project is aimed to build an Open Source Manufacturing Execution System based on J2EE, JBoss technology. Intesity based optimization
    Downloads: 0 This Week
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  • 9
    Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported. Project branch continues to evolve: https://github.com/gburdell/nldb including addition of tclsh UI.
    Downloads: 0 This Week
    Last Update:
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  • 10
    This is an attempt to build an Java GUI for a low cost digital storage oscilosope based on a RS232 interface.
    Downloads: 0 This Week
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  • 11
    Display gerber pcb (RS 273X format) files and drill files.
    Downloads: 4 This Week
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  • 12
    SymtaP is a performance analysis tool to determine the worst case execution time for embedded real time applications.
    Downloads: 0 This Week
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  • 13
    Processes boolean functions which can be provided either as a list of 0s and 1s or which can be provided as a formula in first-order logic (using disjunctive or conjunctive normal forms). Internally the Quine McCluskey algorithm is used.
    Downloads: 0 This Week
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  • 14
    Downloads: 0 This Week
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  • 15
    Java source to C source translator, which allows to write MCU programs in Java. Now AVR are supported, others can be added. Convenient Java methods instead of manual register handling.
    Downloads: 0 This Week
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  • 16
    ExpressLib is a Java library that can read and convert the file format of ExpressSCH/ExpressPCB
    Downloads: 2 This Week
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  • 17
    The aim of this project is to develop a GDSII viewer by using Java programming language. Efforts will be made especially on ease-of-use, efficiency, and capacity.
    Downloads: 0 This Week
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  • 18
    HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
    Downloads: 0 This Week
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  • 19
    PIC Development Studio is a simulator for the PIC16F84 microcontroller. It also provides a plugin framework making it possible to develop custom components. A library of ready-made components is included.
    Downloads: 5 This Week
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  • 20
    Equivalence checking for two netlists of ORCAD schematic designs. Check out whether two netlists may generate the idendical PCB in later design stage, even if they are derived from different design procedures with different part-ref and siganl-name.
    Downloads: 0 This Week
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  • 21
    Generic packet visualization tool for generating flow diagrams from formatted logs. Can be used for cache coherency diagrams, software interaction diagrams or to plot network communications.
    Downloads: 0 This Week
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  • 22

    Circuit Sandbox

    Visually build and simulate boolean logic circuits

    Visually build boolean logic circuits and then simulate their operation. Create custom components from user-designed circuits. Written in Java for cross-platform functionality. NOTE: This project has moved to Bitbucket at http://bitbucket.org/kwellwood/circuitsandbox
    Downloads: 3 This Week
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  • 23
    Project for build a free eletronic/logic simulator as a standalone plataform independent software
    Downloads: 0 This Week
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  • 24
    Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.
    Downloads: 0 This Week
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  • 25
    Trident is a high-level language compiler for scientific agorithms written in C that target FPGAs.
    Downloads: 0 This Week
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