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ChronoSVG generates a timing diagram, as used in electrical devices documentations, from a simple and intuitive ASCII source file. The output file is in SVG format, and makes use of CSS to defer the styling details to presentation time.
This set will able to generate eeschema libraries, parse KiCAD files (eeschema, eeschema library, netlist), generate Russian GOST specifications for schemes and do other actions.
Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported.
Project branch continues to evolve: https://github.com/gburdell/nldb
including addition of tclsh UI.