Search Results for "python::module"
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Showing 29 open source projects for "python::module"
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Free VHDL Parser with Java, Python and T
IEEE VHDL-93 LRM supported parser implemented in Java, APIs Python/Tcl
This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. This tool has... -
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EDAUtils Converters
Free converters across IP-XACT Verilog VHDL Liberty SystemC
...vhdl2verilog : Tool to convert VHDL into Verilog by keeping the same structure and function for ease of correlation verilog2ipxact :Tool to create IP-XACT Component or Design from a Verilog Module. ipxact2verilog : Tool to convert IP-XACT into Verilog module ipxactinterface2svinterface : Converts IP-XACT Bus Definition / BusInterface into System Verilog Interface verilog2lib : Create Liberty .lib library from verilog module lib2verilog : Converts Liberty .lib Cells into empty verilog modules verilog2systemc : Tool to convert Verilog into SystemC keeping the original structure as much as possible. ... -
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1. flattenverilog : Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist. 2. preprocessverilog : Verilog Preprocessor to resolve macros like nested `ifdef , `define 3. createhierarchy : Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents in the higher leve 5. removehierarchy : Verilog Hierarchy Removal Tool to ungroup all the instances in a given module 6. comparemoduleinterfaces - Diff module ports and parameter. ...
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LaSolv
Solves symbolic electrical AC circuit equations
In electrical engineering, AC circuits are often used in the design process. However, deriving the gain, input impedance or what have you is tedious and error prone. LaSolv takes a SPICE like description of your circuit and solves for whatever parameter you specify- voltage gain, trans-impedance, input impedance, etc. -
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Free Parsers for Liberty UPF SDC VCD
Free Liberty, UPF, SDC and VCD Parsers with Python, Java and Tcl APIs
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System Verilog Parser IEEE 1800 LRM
IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the... -
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UMHDL
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So,... -
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dvkit
Eclipse-based IDE for design verification tasks
DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code -
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dxf2pcb
Convert DXF drawings of circuit boards to gEDA-PCB files.
This Python script reads in a DXF (ascii) file and generates a PCB output compatible with PCB Designer, part of the gEDA suite. It is designed for two purposes: One is to generate a PCB snippet from a mechanical drawing (such as a board outline), the other is to produce element files from CAD drawings. PCB snippets are easily imported into an existing gEDA-PCB project using File -> Load Layout to Buffer. -
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DEVSIM
TCAD Device Simulator
TCAD Device Simulator. DEVSIM is a semiconductor device simulation software, using the finite volume method. This software solves partial differential equations on a mesh. The Python interface allows the user to specify their own equations. -
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), OpenAccess, DXF, CIF (Caltech Intermediate Form), ...
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An active filter design assistant. Electrical engineers can use it to design and simulate analog active filters.
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A Step Closer to a Fully Gui ATLAS .log Converter A Gui .in Editor to be Used by ATLAS .log awk converter
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naga EDA devotes to provide useful electronic design tools in C++ and, especially, Python. The current release contains naga.Verilog, a Verilog parser. Please visit project homepage http://naga-eda.org for more information
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Gaphor is a UML modeling environment written in Python. Gaphor is small and very extensible. The repository is located at http://github.com/gaphor/gaphor.
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Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
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OpenMie aims to solve electromagnetic scattering problems via the Mie method to provide a benchmark against which to test more general scattering codes. Complete field solutions are given for a number of practical geometries.
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PyPCB is a Python package for working with PCB (http://pcb.sourceforge.net) files. PyPCB can be used to create new useful tools, as footprint generators or library managers.
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Processes boolean functions which can be provided either as a list of 0s and 1s or which can be provided as a formula in first-order logic (using disjunctive or conjunctive normal forms). Internally the Quine McCluskey algorithm is used.
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pyLPCTools is a replacement for the Flash Programming Tools use with the Philips(tm)/NXP(tm) LPC2xxx series of ARM based microcontrollers. pyLPCTools is a script together with some ARM assembly language and a Python user interface. Please Donate !!
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Sk2Py is an wxPython-based IDE which assists in the migration of Cadence Skill(tm)-based PCells to Python PyCells for use in all Open Access environments. Please post any support requests or bug reports to the tracking system.
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GerbTool is a set of tools for modifying gerber and excellon drill files. GerbTool can be used to tile multiple gerber files as a single job, and can be run interactively or in batch mode.
