Search Results for "pentesting operating system"
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Showing 37 open source projects for "pentesting operating system"
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AUDio MEasurement System
PC based Oscilloscope and Spectrum analyzer using sound card
AUDio MEasurement System - a multi-platfrom system for audio measurement through sound card in the PC. It contains: generator, oscilloscope, audio spectrum analyzer (FFT) and frequency sweep plot. Compiles and works under Linux, Windows and MacOS. Source code is available in "git" and as ZIP snapshot. For more information see README.md -
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Ngspice project aims to improve the spice3f5 circuit simulator.
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VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
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XSCHEM
Schematic circuit editor for VLSI and Mixed mode circuit simulation.
Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this... -
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A portable loudspeaker design system supporting measurement, modeling, simulation and optimization of boxes, filters and systems.
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wxArt2D gives wxWindows applications sophisticated vector drawing functionality. It is based on a framework supporting multiple views within a hierarchical document. Supports drawing & (Graph) editing. In-output in SVG, GDSII, XML, easy to extend.
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IEC 60870-5 104 Protocol download
IEC 104 RTU Server Client Simulator Source Code Library Win Linux
v21.06.018 Complete implementation of iec 104 protocol standard including File transfer. Make your RTU, protocol converter, Gateway, HMI, Data concentrator compatible with iec 104. *Industry Proved * Worldwide Customers Download Evaluation Kit - IEC 104 Development Bundle In the Development Bundle, We included IEC 104 Server & Client Simulator, Windows & Linux... -
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PCB is a tool for the layout of printed circuit boards. PCB can produce industry standard RS-274X and Excellon NC-Drill format output for submission to board manufacturers.
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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KiCAD5 Live USB
A Cross Platform and Open Source Electronics Design Automation Suite
A Cross Platform and Open Source Electronics Design Automation Suite Live USB. -
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Resistor Value Identifier
Identify electronic resistor values
This HTML utility allows the user to select standard color codes or surface mount numbers, then it identifies the resistor value. There is no need to memorize color codes or multipliers. An online working example of this program can be used at ZoomAviation.com/programs. -
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ArchC is an open-source architecture description language based on SystemC. Its goal is to provide designers with a tool to evaluate new ideas in processor and ISA design, memory hierarchy, etc. and other aspects of computer architecture research.
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The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types, such as logic analyzers, MSOs, oscilloscopes, multimeters, LCR meters, sound level meters, thermometers, anemometers, light meters, dataloggers, function generators, power supplies, GPIB interfaces, and more.
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An Electronic Definition Interchange Format (EDIF) parser which allows exports from one EDA schematic capture system (such as OrCad) for import into another (such as KiCad)
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ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.
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IMPORTANT: The flosslogic project has merged with the sigrok project. Development continues in the sigrok wiki, mailing lists, IRC channel, and git repository.
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Wcalc is a tool for the analysis and synthesis of electronic components. Some of the models include coupled microstrip lines, single layer air core solenoid inductors, etc. Wcalc can analyze the electrical parameters based on the physical dimensions a
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The SESAME (Simulation of Embedded System Architectures for Multilevel Exploration) software system is an embedded system co-simulation environment and research tool which implements the ideas of the SESAME project at the University of Amsterdam.
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HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
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Spice+ is a general-purpose circuit simulation program, based directly on SPICE 3F.5 from the University of California (Berkeley). An improved version of Spice for DOS, Windows and Linux. http://spicep.sourceforge.net
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The comprehensive C++ library MGEN for IC layout and connectivity comes with the X11/Motif full custom layout editor PARIS and the powerful waveform viewer/processor MANIAC. Industry proven, it is the basis for layout generators, placers, routers etc.
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A UNIX/X11 circuit drawing application with schematic capture. Features user-definable parts libraries and fully hierarchical SPICE netlist generation.
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A Hardware/Software Co-Simulation package utilizing TCP/IP networking to allow C and Perl based development simulation environments using Verilog or SystemC hardware models.
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The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.
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Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.
