Search Results for "java profiler windows" - Page 3
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Showing 102 open source projects for "java profiler windows"
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ElectroMimic is an electronic circuit simulator in Java™. The simulator is focused on the piecewise-linear models normally used by undergraduate students, but can also be linked with external simulation software for more realistic results.
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This project is aimed to build an Open Source Manufacturing Execution System based on J2EE, JBoss technology. Intesity based optimization
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Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported. Project branch continues to evolve: https://github.com/gburdell/nldb including addition of tclsh UI.
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This is an attempt to build an Java GUI for a low cost digital storage oscilosope based on a RS232 interface.
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SymtaP is a performance analysis tool to determine the worst case execution time for embedded real time applications.
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Processes boolean functions which can be provided either as a list of 0s and 1s or which can be provided as a formula in first-order logic (using disjunctive or conjunctive normal forms). Internally the Quine McCluskey algorithm is used.
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Java source to C source translator, which allows to write MCU programs in Java. Now AVR are supported, others can be added. Convenient Java methods instead of manual register handling.
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The aim of this project is to develop a GDSII viewer by using Java programming language. Efforts will be made especially on ease-of-use, efficiency, and capacity.
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HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
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Equivalence checking for two netlists of ORCAD schematic designs. Check out whether two netlists may generate the idendical PCB in later design stage, even if they are derived from different design procedures with different part-ref and siganl-name.
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PIC Development Studio is a simulator for the PIC16F84 microcontroller. It also provides a plugin framework making it possible to develop custom components. A library of ready-made components is included.
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Generic packet visualization tool for generating flow diagrams from formatted logs. Can be used for cache coherency diagrams, software interaction diagrams or to plot network communications.
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Circuit Sandbox
Visually build and simulate boolean logic circuits
Visually build boolean logic circuits and then simulate their operation. Create custom components from user-designed circuits. Written in Java for cross-platform functionality. NOTE: This project has moved to Bitbucket at http://bitbucket.org/kwellwood/circuitsandbox -
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Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.
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Open framework for the automated synthesis of integrated heterogeneous (analog and multi-domain) systems.
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Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.
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The official repository of JCSim is now hosted by github at https://github.com/almejo/jcsim JCSim is a fully functional Digital Circuit simulator written in Java. You can create and simulate simple (and not so simple) circuits in an easy way. It includes a basic set of gates, simple creation of new gates and simulation.
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mcuStudio is a development environment for Microcontrollers. It's based on Eclipse (plugin). The aim is to provide a high quality development environment for electronics. First editions will target Microchip Pic mcu's. Other mcu will be supported later.
