9 projects for "git:/git.code.sf.net/p/docfetcher/code" with 2 filters applied:

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  • 1

    AUDio MEasurement System

    PC based Oscilloscope and Spectrum analyzer using sound card

    AUDio MEasurement System - a multi-platfrom system for audio measurement through sound card in the PC. It contains: generator, oscilloscope, audio spectrum analyzer (FFT) and frequency sweep plot. Compiles and works under Linux, Windows and MacOS. Source code is available in "git" and as ZIP snapshot. For more information see README.md
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    Downloads: 76 This Week
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  • 2
    BuddyCAD

    BuddyCAD

    A set of freeware applications for viewing/processing P-CAD files.

    BuddyCAD Viewer+ can view/process files for following P-CAD versions: - P-CAD v4.5 - P-CAD v8.5 / v8.7 / v9.0 - P-CAD 99 / Accel / 2002 / 2004 / 2006 (through ASCII import)
    Downloads: 0 This Week
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  • 3
    TinyCAD
    ...It supports PCB layout programs with several netlist formats and can also produce SPICE simulation netlists. It is also often used to draw one-line diagrams, block diagrams, and presentation drawings. The source code for TinyCAD is now on GitHub: https://github.com/matt123p/TinyCAD Online documentation can be found here: https://github.com/matt123p/TinyCAD/wiki
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    Downloads: 1,128 This Week
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  • 4
    eLogSim

    eLogSim

    Digital circuit simulator

    ...It uses a test oriented stimulus approach and offers a statistical (or exhaustive if it makes sense) fault simulation option. eLogSim has a simple GUI and is pre-compiled for Ubuntu 20, Mint 20, CentOS 8, openSUSE 15, FreeBSD 12, Solaris 11, Windows 10/11 & Raspbian/Raspberry PiOS Buster (32/64bit) & Ubuntu-MATE 20.04 (64 bit) operating systems. Cross platform & -network, concurrent fault simulation now available. Commented, easy-to-compile source-code included as well.
    Downloads: 0 This Week
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  • 5

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    ...On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 1 This Week
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  • 6
    adms
    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
    Downloads: 11 This Week
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  • 7
    ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.
    Downloads: 0 This Week
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  • 8
    IMPORTANT: The flosslogic project has merged with the sigrok project. Development continues in the sigrok wiki, mailing lists, IRC channel, and git repository.
    Downloads: 0 This Week
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  • 9
    asfpga is an assembler written for use in FPGA design. It can be easily modified for your instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set. The current version al
    Downloads: 0 This Week
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