Search Results for "linux command"

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

v21.06.018 Complete implementation of iec 104 protocol standard including File transfer. Make your RTU, protocol converter, Gateway, HMI, Data concentrator compatible with iec 104. *Industry Proved * Worldwide Customers Download Evaluation Kit - IEC 104 Development Bundle In the Development Bundle, We included IEC 104 Server & Client Simulator, Windows & Linux...

gputils is a collection of tools for Microchip PIC microcontrollers. Its goal is to be fully compatible with Microchip's tools, MPASM, MPLINK, and MPLIB.

UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It is a descendant of the popular openwince JTAG tools with a lot of additional features and enhancements.

The ASCO project aims to bring circuit optimization capabilities to existing SPICE simulators using a high-performance parallel differential evolution (DE) optimization algorithm. It supports Eldo, HSPICE, LTspice, Spectre, and Qucs.

A program that generates PLD (Programmable Logic Device) programming tables & LFSR/BIBLO (Linear Feedback Shift Register/Built In Logic Block Observer) signature for a function given by the user.

Convert from Qucs Pr1.v dataset to Audacity equalization curve xml. Tested with Qucs Dataset 0.0.18 and Audacity 2.0.3

ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git

GHDL is the leading open source VHDL simulator. *** Now on github.com/tgingold/ghdl *** We have binary distributions for Debian Linux, Mac OSX and Windows. On other systems, getting GHDL from here means downloading the current source package and building GHDL from source. Alternatively you can get the latest source version (warning : occasionally unstable!) by pulling a snapshot from the git repository.

Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)

This (Python) tool allows you to easily create FPGA bitfiles for your embedded system, from several Open Source IPs (compatibles with the OpenCores Wishbone bus) . It will also generates the corresponding drivers (currently only Linux ones).

It is a software to program ISP based 8051 controllers(89SXX) on Linux. The software decodes the hex file entered from the command line and send it to controller's flash memory using PC's parallel port.The hardware connections are very minimal.

During the period from 1990 through 2002, EPRI funded the development of a Lightning Protection Design Workstation (LPDW), which was used by many utilities to assess the lightning performance of distribution lines. Since about 2002, this program has not been available. EPRI decided to release the simulation kernel of LPDW under an open-source license (GPL v3), so it may be incorporated into IEEE Flash and other projects. OpenETran can presently simulate multi-conductor power lines,...

FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info in wiki.

Framework for the Analysis and Modification of EDIF netlists (FAME) is a C++ framework, developed at Politecnico di Torino, aimed at automating the analysis and modification of complex circuit netlists described in the standard EDIF 2.0.0 language.

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered

IMPORTANT: The flosslogic project has merged with the sigrok project. Development continues in the sigrok wiki, mailing lists, IRC channel, and git repository.

This project is for converting PCB RS274X gerber files to RS274NGC Gcode files. Currently this software is in the early development stages. Currently working to simplify the program and improve reliability.

Sister is high-level synthesizer for SoC design . It analyzes SystemC(based on C++ language) source code and creates Verilog HDL source code.

InSystem Serial Programmer Fujitsu MCU F2MC-16LX and FR series.

PicOload is a programmer and a bootloader that allow to program a PIC 16f87X / 16f87XA using a RS232 serial line whithout leaving the chip from his support and without disturbing the rest of the device

A cross-platform simulator for embedded systems, with a plug-in architecture for adding microcontrollers and other devices. Written in C for maximum compatibilty and speed. Currently has support for AVR AT90S8515 and ATmega128.

Programmer for Atmels 8051 devices, parallel Flash and E2PROM memories and etc.

ICDPROG is a simple command line programmer for Microchip PIC controllers, using the Microchip ICD (in circuit debugger) as a programmer.

Portatux is an interactive ncurses interface as well as a command line tool for controlling the 8 data pins in the parallel port in Linux and FreeBSD.