Search Results for "simulation software"
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Showing 20 open source projects for "simulation software"
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Quite Universal Circuit Simulator
A circuit simulator with graphical user interface (GUI)
Qucs is a circuit simulator with graphical user interface. The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter, Transient, Noise and Harmonic Balance analysis. Pure digital simulations are also supported. -
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IEC 60870-5 104 Protocol download
IEC 104 RTU Server Client Simulator Source Code Library Win Linux
... http://www.freyrscada.com/iec-60870-5-104-Client-Simulator.php http://www.freyrscada.com/iec-60870-5-104-Windows-Software-Development-Kit(SDK).php http://www.freyrscada.com/iec-60870-5-104-Linux-Software-Development-Kit(SDK).php Video Tutorial https://www.youtube.com/playlist?list=PL4tVfIsUhy1bx7TVjtZnqFB6tbZBhOlJP -
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simutron
AVR simulator IDE
Electronic circuit simulator. Simple environment to run and debug firmware for AVR 8-bit microprocessors. Able to run arduino firmware. Internally this program uses the open source Simavr AVR Processor Simulator (https://github.com/buserror/simavr) and wraps all its functions in a GUI shell. Setups for firmware debugging scenarios can be created dynamically. Able to run 16MHz MCU with decent set of external parts in real time. In particular this can be used for development of CNC firmware... -
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Caneda
Caneda (Circuits and Networks EDA) is an open source EDA software.
Caneda (Circuits and Networks EDA) is an open source EDA software focused on easy of use and portability. While in the short term schematic capture and simulation is the primary goal, in the long term future, PCB and layout edition will be covered. -
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DEVSIM
TCAD Device Simulator
TCAD Device Simulator. DEVSIM is a semiconductor device simulation software, using the finite volume method. This software solves partial differential equations on a mesh. The Python interface allows the user to specify their own equations. -
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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These classes are useful for signal processing in Matlab or C++. They bring together tools and methods which may be used interchangeably for Matlab and C++. Their initial use is in conjunction with work towards my degree at UC Berkeley.
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LSim is a software for simulation and make executables to ARM Cortex-M3 mcu from logic gates diagram. LSim can compile logic gates diagram and generate binary executable files (*.bin, *.hex) for cortex-m3 mcu´s (LPC1768, under development).
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Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.
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ENIAC: Electrical Network Interactive Analysis Console. Educational software originally made for the study and simulation of electrical LTI circuits, but which supply also a lot of mathematics computations, like complex, polynomial and matrix operations.
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The SESAME (Simulation of Embedded System Architectures for Multilevel Exploration) software system is an embedded system co-simulation environment and research tool which implements the ideas of the SESAME project at the University of Amsterdam.
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This is a tool developed by 2nd yr CSE B.Techs at IIT Guwahati.We have designed a software in C++ language which,given some design specifications of an analog amplifier generates a netlist file in the current folder which can be opened in LTSpice.
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QUASI is stand-alone AVR RISC processor simulator with debugging features, EDA-like GUI and plugin interface.
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Software I/O Digital Analyzer and Digital Input/Output Simulator for electronics experiments. It's also a 16 digital channel data logger. Hardware supported: Ethernet I/O Card , USB I/O Card and Parallel Interface.
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A Hardware/Software Co-Simulation package utilizing TCP/IP networking to allow C and Perl based development simulation environments using Verilog or SystemC hardware models.
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ESOMA is a component orientated framework for simulation and evaluation of arbitrary microprocessor and DSP architectures. Simulators using ESOMA are runtime configurable. Architectural changes do not need recompiling. Programming language is C++ (Linu
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Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
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UVE
Unified Verification Environment
The aim of the UVE project is to create software that automatically generates a verification testbench (TB) written in SystemVerilog (SV) and integrating the UVM methodology. UVE makes the rapid development of a verification environment a simple process. The generated TB is directly able to perform random actions on the DUV (design under verification). For this UVE provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One...
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