IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
A graphical Finite State Machine (FSM) designer.
Labcoat; the VHDL graphic emulator.