Search Results for "compiler python linux"
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Showing 77 open source projects for "compiler python linux"
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Define and Deliver Comprehensive Cybersecurity Services. Security threats continue to grow, and your clients are most likely at risk. Small- to medium-sized businesses (SMBs) are targeted by 64% of all cyberattacks, and 62% of them admit lacking in-house expertise to deal with security issues. Now technology solution providers (TSPs) are a prime target. Enter ConnectWise Cybersecurity Management (formerly ConnectWise Fortify) — the advanced cybersecurity solution you need to deliver the managed detection and response protection your clients require. Whether you’re talking to prospects or clients, we provide you with the right insights and data to support your cybersecurity conversation. From client-facing reports to technical guidance, we reduce the noise by guiding you through what’s really needed to demonstrate the value of enhanced strategy.
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Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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Free VHDL Parser with Java, Python and T
IEEE VHDL-93 LRM supported parser implemented in Java, APIs Python/Tcl
This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. This tool has... -
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UMHDL
Integrated Development Environment (IDE) for learning HDL
..., the interface developed acts as a front-end that allows writing code (with syntax highlighting), invokes an external VHDL compiler and simulator (such as GHDL), and displays the result of the simulation graphically as waveforms (invoking to GTKWave). -
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CircuiTikZ Generator
This software is a tool for designing electronic circuits using LaTeX.
This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library. -
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IEC 60870-5 104 Protocol download
IEC 104 RTU Server Client Simulator Source Code Library Win Linux
v21.06.008 Complete implementation of iec 104 protocol standard including File transfer. Make your RTU, protocol converter, Gateway, HMI, Data concentrator compatible with iec 104. *Industry Proved * Worldwide Customers Download Evaluation Kit - IEC 104 Development Bundle In the Development Bundle, We included IEC 104 Server & Client Simulator, Windows & Linux SDK. http://www.freyrscada.com/iec-60870-5-104.php http://www.freyrscada.com/iec-60870-5-104-Server-Simulator.php http... -
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eavref
A tool for low-power CMOS voltage reference designs
EAVREF is a computer-aided tool for robustly designing ultra-low-power CMOS voltage references. The tool is compatible with the powerful Ngspice simulator, enabling open-source microelectronics design flow with SkyWater 130nm Technology. -
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LaSolv
Solves symbolic electrical AC circuit equations
In electrical engineering, AC circuits are often used in the design process. However, deriving the gain, input impedance or what have you is tedious and error prone. LaSolv takes a SPICE like description of your circuit and solves for whatever parameter you specify- voltage gain, trans-impedance, input impedance, etc. -
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Baya - SoC Integration Platform
Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity database with... -
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Free Parsers for Liberty UPF SDC VCD
Free Liberty, UPF, SDC and VCD Parsers with Python, Java and Tcl APIs
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ConnectWise SIEM (formerly Perch) offers threat detection and response backed by an in-house Security Operations Center (SOC). Defend against business email compromise, account takeovers, and see beyond your network traffic. Our team of threat analysts does all the tedium for you, eliminating the noise and sending only identified and verified treats to action on. Built with multi-tenancy, ConnectWise SIEM helps you keep clients safe with the best threat intel on the market.
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IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support... -
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System Verilog Parser IEEE 1800 LRM
IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the... -
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GLogic
A logic gate simulator for linux developed with Gtk and python.
GLogic is a logic gate simulator for linux and an adaptation of the gLogic package.... -
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FreeCAD-PCB
Import your PCB boards to FreeCAD
[ENG] Mod FreeCAD-PCB allow you to import PCB boards to FreeCAD. Scope of mod: - support for many different layers, - possible to choose colours, transparency and names for each layer, - mod allows you to import IGES models with colours, - possible to show holes/vias independent. [PL] Moduł FreeCAD-PCB pozwala na importowanie płytek PCB do programu FreeCAD. Możliwości modułu: - wsparcie dla wielu różnych warstw, - wyświetlanie otworów, przelotek niezależnie od siebie, - możliwość... -
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dvkit
Eclipse-based IDE for design verification tasks
DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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My Beaglebone Black Project
show and configure
The Beaglebone Black project presented here is a software written by Python and Qt and is intended to show the simple control of inputs and outputs (GPIO), the graphic course of input signals GPIO, the configuration and sending and receiving of data via the UART interfaces, the display of the PIN configuration of the Beaglebone Black and the graphic display of the signal course at the analog inputs. The software runs on the BBB under Debian 8.9 and on Linux computers (as a demo). It is intended... -
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pyGerber2Gcode
Python Gerber to G-code converter
pyGerber2Gcode is a Pyhon based simple Gerber to G-code converter. -
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dxf2pcb
Convert DXF drawings of circuit boards to gEDA-PCB files.
This Python script reads in a DXF (ascii) file and generates a PCB output compatible with PCB Designer, part of the gEDA suite. It is designed for two purposes: One is to generate a PCB snippet from a mechanical drawing (such as a board outline), the other is to produce element files from CAD drawings. PCB snippets are easily imported into an existing gEDA-PCB project using File -> Load Layout to Buffer. Generated element files are ready to use (except for special cases like no-paste flags... -
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O.N.O.S
Open Network Object System
Open Network Object System A Internet of things Content management system. Would you like to automate and controll remotely your home appliances from internet or lan using your phone /pc ? This program is for you! Internet of things made easy for everyone. Open source , simple to use , no need to know any programming language , you can add your programs easy , it runs bash command!every linux system will run it , portable . No installation required! just copy the folder where you want... -
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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DEVSIM
TCAD Device Simulator
TCAD Device Simulator. DEVSIM is a semiconductor device simulation software, using the finite volume method. This software solves partial differential equations on a mesh. The Python interface allows the user to specify their own equations. -
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This (Python) tool allows you to easily create FPGA bitfiles for your embedded system, from several Open Source IPs (compatibles with the OpenCores Wishbone bus) . It will also generates the corresponding drivers (currently only Linux ones).
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Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
... have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. We believe the use of an HDL is also the way of the future when it comes to PCB design. The PHDL compiler automatically supports the output of PADS and Eagle netlists, and through extending a simple java class, users can generate a netlist in practically any format required by their choice of a layout tool.