Search Results for "c-bus" - Page 7
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Showing 399 open source projects for "c-bus"
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From improving customer experience through seamless sign-on to making MFA as easy as a click of a button – your login box must find the right balance between user convenience, privacy and security.
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Interactive viewer for ngspice raw files. Provide interface to view analog waveforms, results of ngspice simulator. Allows printing, saving as image, copy to clipboard. Uses wxWidget, but heavily tailored to UNIX OS. Tested on Ubuntu 10.04
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This is a simple viewer for the ``Stream Format'' for CALMA GDSII CAD libraries (``GDS II'', ``.gds'' or ``.sf'') with a couple of limitations. The main functionality is viewing the library layers with different colors.
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These classes are useful for signal processing in Matlab or C++. They bring together tools and methods which may be used interchangeably for Matlab and C++. Their initial use is in conjunction with work towards my degree at UC Berkeley.
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Boost application security and continuity with SKUDONET ADC, our Open Source Load Balancer, that maximizes IT infrastructure flexibility. Additionally, save up to $470 K per incident with AI and SKUDONET solutions, further enhancing your organization’s risk management and cost-efficiency strategies.
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This project has been abandoned. Please go to https://github.com/xesscorp for current open source offerings from XESS Corp.
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Gnetman is primarily a netlist translator, capable of translating between formats such as VHDL, Verilog, and SPICE. Only structural gate-level netlists are supported. Various netlist manipulations are supported.
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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
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Projeto para controle da porta paralela em Linux. Este projeto pode ser utilizado como integrador em projetos de robotica ou automação industrial. Funciona na console e permite integração com diversas linguagens como java/php/c++ entre outras.
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Red Hat Enterprise Linux (RHEL) on Microsoft Azure provides a secure, reliable, and flexible foundation for your cloud infrastructure. Red Hat Enterprise Linux on Microsoft Azure is ideal for enterprises seeking to enhance their cloud environment with seamless integration, consistent performance, and comprehensive support.
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The Virtual Electronics Library, or VE-Lib, is a C++ library used to easily add electronic simulation in your programs. It makes use of the scripting language Lua to easily add new components like new resistors and microchips.
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Digital Signal Processing Block Diagram Compiler - user extendable to all DSP's, but presently supports only the TI C2000 family. Rich support for fixed point arithmetic, both saturated and unsaturated. Block diagram entry is via TinyCAD (included).
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Lossi (LOgikSchaltungsSImulator - german for "logic circuit simulator"). It simulates logic circuits. Really.
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Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
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GEZEL is a cycle-based hardware description language. The GEZEL tools offer stand-alone - and cosimulation, and code-generation into VHDL code. User-defined library-block extensions in C++ allow to add new cosimulation/cosynthesis interfaces.
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LSim is a software for simulation and make executables to ARM Cortex-M3 mcu from logic gates diagram. LSim can compile logic gates diagram and generate binary executable files (*.bin, *.hex) for cortex-m3 mcu´s (LPC1768, under development).
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pgmtokicad is a project that aims to develop and maintain applications that can be useful for importing custom images in both schematics and printed circuit boards made with KiCAD
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The ixo.de USB JTAG pod and firmware allows to access JTAG-capable chips via USB and a protocol like Altera USB-Blaster.
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Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.
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Liquid PCB is a Computer Aided Design (CAD) application for designing Printed Circuit Boards. It is unlike any PCB CAD package you have used before. It has innovative user interface, and lets you create freeform tracks without any straight lines.
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Visualization of PCB (printed circuit board) descriptions in Gerber RS-274X format. The intention is to let a PCB designer take an RS-274X formatted file and generate a 3D concept view, either locally, or generated as PNG/clip, or browsable X3D/VRML.
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SCLive is a modular Linux-Live Distribution dedicated to the OSCI SystemC simulator and it's associated libraries. The distribution provides a fully working environement including a simulator kernel, wavefom viewer, IDE, tutorials and more.
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IMPORTANT: The flosslogic project has merged with the sigrok project. Development continues in the sigrok wiki, mailing lists, IRC channel, and git repository.