Search Results for "user mode linux" - Page 2

The ASCO project aims to bring circuit optimization capabilities to existing SPICE simulators using a high-performance parallel differential evolution (DE) optimization algorithm. It supports Eldo, HSPICE, LTspice, Spectre, and Qucs.

VISTAS (VCSEL Integrated Spatio-Temporal Advanced Simulator) is a highly efficient 2D, time-domain Vertical-Cavity Surface-Emitting Laser (VCSEL) model aimed at optimizing entire optical links.

... in conjuction with its CAM frontend without access to the real hardware. For Linux and Windows systems. Please visit wiki pages (https://sourceforge.net/p/simutron/wiki/Home/) for instructions

A multiplatform vector drawing program with a complete library of electronic symbols. Schematics and drawings are stored in a very compact text format. There is no netlist concept behind the drawings (so no simulation, and this is a choice) but this allows a great graphical flexibility and ease of use, making FidoCadJ the perfect tool for exchange sketches in forum and newsgroup discussions with a few clicks. Drawings can be exported in several graphic formats, such as pdf. Follow the...

A simple VHDL(VHSIC Hardware Description Language) preprocessor

Gerber2eps - A small program for converting Gerber RS-274D files to Encapsulated Postscript (EPS).

vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.

Distributed test running system. build for running simulations, quality assurance or similar where you need to run a large number of tests. Supports dependencies, iteration, disk space management and log file analysis.

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

A program that generates PLD (Programmable Logic Device) programming tables & LFSR/BIBLO (Linear Feedback Shift Register/Built In Logic Block Observer) signature for a function given by the user.

Gerbv is an open source Gerber file (RS-274X only) viewer. Gerbv lets you load several files on top of each other, do measurements on the displayed image, etc. Besides viewing Gerbers, you may also view Excellon drill files as well as pick-place file

DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code

SVEditor is an Eclipse-based IDE (Integrated Development Environment) for SystemVerilog and Verilog files. It features syntax coloring, content assist, source indent and auto-indent, and structure display.

Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.

Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.

xc3sprog is a suite of utilities for programming Xilinx FPGAs, CPLDs, and EEPROMs with the Xilinx Parallel Cable and other JTAG adapters under linux. Originally based on code written by Andrew Rogers (http://www.rogerstech.co.uk/ ).

Convert from Qucs Pr1.v dataset to Audacity equalization curve xml. Tested with Qucs Dataset 0.0.18 and Audacity 2.0.3

Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.

Ycad is a library of CAD functions in Java. Currently only DXF is supported for reading, viewing and writing. The DXF drawing may be rendered to a Graphics object for printing or imaging.

Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.

Circuitmod is a circuit simulator that extend the capacity of the original Falstad's Java Circuit Simulator into CMOS Chips, Led Arrays, Led Matrix and PIC Programming. The Horizon is limitless. Try today.

Analog Insydes is a Mathematica toolbox for symbolic analysis of analog electronic circuits. This project provides a set of free add-ons to Analog Insydes, including a Java front-end and a native netlister for Cadence's Analog Design Environment (ADE).

ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git

GNUSim8085 is a simulator and assembler for the Intel 8085 Microprocessor. For downloading latest release please head to the website - https://gnusim8085.github.io/ For source code - https://github.com/GNUSim8085/GNUSim8085

COTSon scalable simulation infrastructure