Open-source code generator for Simulink/Stateflow
C++ CASE tool, full life cycle code generator
Describe and watch component structure of java programs
A graphical Finite State Machine (FSM) designer.
Busilet is a reference implementation of IDTP and UTID.
Repository for dependencies between software design artefacts
Software Modularization and Monitoring Tool
VHDL Design Tool - code generation and project management