Search Results for "verilog-a"

Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.

Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation.

Application defines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.

vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.

ACMgen is an automatic code generator of Asynchronous Communications Mechanisms based on the generation of Petri nets models that can be formally verified against some properties and then transformed into a real implementation (e.g. C++ or Verilog).