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ALCHA aims to reduce FPGAproject develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides.
It will support an object oriented programming model, abstract data and signal types, and compile-time scripting.
Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.
Demo of Simulink to C++ C or HDL FGA for HFT potential
Video and files download for Visual trading idea to C++ or FPGA HFT Meetup
File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated)
Powerpoint MATLAB SIMULINK
http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/
GIAnT (Generic Implementation ANalysis Toolkit) is a platform for physical analysis of (embedded) devices. Primarily designed for hardware security analyses, it is built around an FPGA-based board for fault injection and side-channel analysis.
This project has been supported by the German Federal Ministry of Education and Research BMBF (grant 01IS10026A, Project EXSET).
...Development of SAA SOUND began around 1996 with active development ceasing around 2001.
Interest increased in August 2018 with the original author now revisiting the project after a considerable time.
It has been incorporated into standalone chiptune players, computer hardware emulators (e.g. SimCoupe), and has even been the basis of SAA-1099 hardware emulators implemented in FPGA devices (such as MiST / MiSTer)
Moved permanently to:
https://github.com/stripwax/SAASound/
This project aims at using the Artificial Intelligence (AI) algorithm called the Genetic algorithm to solve the problem of placement in the FPGA circuits.
This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.
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