Search Results for "gss-api"

...Dynamically recognize modules and strings. Import reconstructor integrated (Scylla). Fast disassembler (Zydis). User database (JSON) for comments, labels, bookmarks, etc. Plugin support with growing API. Extendable, debuggable scripting language for automation. Multi-datatype memory dump. Basic debug symbol (PDB) support. Dynamic stack view. Built-in assembler (XEDParse/asmjit). Executable patching and analysis. We provide both the executable and the source. Feel free to contribute. Write plugins in C++, change colors and tweak your preferences. x64dbg can debug both x64 and x32 applications. ...

REDasm is a cross platform disassembler and binary analysis tool, built for both hobbyists and professional reverse engineers. It supports various CPU architectures and executable formats and also offers an interactive listing, control flow graph view, cross-references, string detection and automatic function recovery. [SUPPORTED FILE FORMATS] PE, ELF, MZ, NE, LE, PSX-EXE, PSX-BIOS, XBE (Xbox), ZX Spectrum (SNA, Z80, TAP), iNES (mapper 0 only) [SUPPORTED...

An open-source x64/x32 debugger for windows. Development is done on GitHub (https://github.com/x64dbg/x64dbg). Daily snapshots are uploaded here, snapshots for every commit can be found on http://releases.x64dbg.com

UniSIMD assembler is a high-level C/C++ macro assembler framework unified across ARM, MIPS, POWER and x86 architectures. It establishes a subset of both BASE and SIMD instruction sets with clearly defined common API, so that application logic can be written and maintained in one place without code replication. The assembler itself isn't a separate tool, but rather a collection of C/C++ header files, which applications need to include directly in order to use. At present, Intel SSE/SSE2/SSE4 and AVX/AVX2/AVX-512 (32/64-bit x86 ISAs), ARMv7 NEON/NEONv2, ARMv8 AArch32 and AArch64 NEON, SVE (32/64-bit ARM ISAs), MIPS 32/64-bit r5/r6 MSA and POWER 32/64-bit VMX/VSX (little/big-endian ISAs) are mostly implemented (/w horizontal reductions) although scalar improvements, wider SIMD vectors with zeroing/merging predicates in 3/4-operand instructions are planned as extensions to current 2/3-operand SPMD-driven vertical SIMD ISA. ...