Search Results for "mpi-sylte noc simulator"

Integrated component-based and cellular automata (CA) Parallel DEVS simulator: https://acims.asu.edu/devs-suite/ OFFERS: 1) synchronized execution & animation, 2) run-time linear/superdense I/O & state trajectories, 3) Action Level Real-Time modeling & simulation, 4) model checking, 5) ABM, 6) CA & composable CA playback, 7) KIB interaction modeling, 8) hierarchical model libraries, 9) Black-Box testing & debugging, 10) PostgreSQL repository, 11) FMU (OpenModelica), 12) OSATE (AADL...

LAMMPS is a classical molecular dynamics simulator designed for parallel machines. It can model atomic, polymeric, biological, metallic, or mesoscale systems using a variety of force fields and boundary conditions and is easy to modify or extend.

The gem5-STNoC model available here (https://sourceforge.net/projects/gem5-stnoc) in alpha version is adapted from the gem5 Garnet Fixed Pipeline as a cycle-approximate NoC model based on STMicroelectronics STNoC backbone specifications. It supports several mechanisms implemented at the STNoC Network Interface, such as NoC Firewall and preliminary Memory Interleaving. The model is freeware covered by standard gem5 license. Development has been partly supported by EU-ICT projects DREAMS...

Paris, or ParisSimulator, is a PArallel Robust Interface Simulator. It combines VOF and Front-Tracking to create simulations of interfacial fluid flow, such as droplet bubbles or waves. It computes complex flows such as fast atomizing jets and has a Lagrangian particle option.

A networks-on-chip (NoC) simulator allows designers to early estimate performance (latency and throughput), energy efficiency (average/peak power, average energy per packet) and area of several networks on-chip configurations at different CMOS nodes. This tool is a cycle-accurate simulator and is open-source using SystemC, a C++ plugin, which is used to quickly model complex systems at a higher level but less details than RTL. NoCTweak was developed by Dr. Anh Tran and Dr. Bevan Baas at UC...

... testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)

We release a simulator for Network-on-Chip (NoC) based manycore systems developed using UNISIM (http://unisim.org) (SystemC CLM) during Xiongfei's study at CHiPES (http://www.chipes.ntu.edu.sg), Nanyang Technological University, Singapore.

This project is about building a simulator for multi-core and NoC systems.

A new simalator for Network-on-Chip which takes advantage of MPI.

SIM-MPI is a trace-driven simulator which can be used for performance prediction of large scale parallel program based on MPI library. SIM-MPI is based on Lo2gGP model which can capture the software overhead in high level communication library.