The goal of this project is to develop an easily modifiable combination of VHDL firmware and LabView drivers for use with laboratory automation control and data acquisition using Terasic's DE2 board and the ISP1362 USB interface chip.
This project succeeds at creating a standalone interface to ISP1362 chip on DE2 board without using the Nios II processor. However, this project suffers from some common pitfalls of hardware design, namely: Compiling this project with Quartus 11 & 12 results in FMAx of 12 MHz, however the minimum clock frequency that the design is supposed to operate safely is 25MHz. The fact that it worked on my board could be attributed to Quartus Timing Analyzer reporting worst case Fmax - but knowing that there is no margin means that this will not work for all boards. -Using the output of a flip flop to drive a clock input of a flip flop - not a good practice on FPGAs - especially if you want to interface the design with other code that is synchronous to the same source clock. - Strong coupling - the entire functionality is placed into one big state machine, which is difficult to maintain, and the design takes a very long time to elaborate. I have used this project as a reference to implement a standalone USB interface to DE2 board. My project can be found here: mzakharo.github.com/usb-de2-fpga/ It alleviates problems mentioned above, and can be used in many areas where simple and reliable communication with PC is required without having to rely on UART.