sim-sim

alpha
4.0 Stars (4)
7 Downloads (This Week)
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Description

HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL

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ease 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 5 / 5
features 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 4 / 5
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support 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 2 / 5
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User Reviews

  • frewcen
    1 of 5 2 of 5 3 of 5 4 of 5 5 of 5

    sim-sim is perfect tool for synthesis, although I have noticed some problems with output formatting, netlist optimalization and absence of documentation.

    Posted 10/02/2013
  • xtofb
    1 of 5 2 of 5 3 of 5 4 of 5 5 of 5

    This is AWESOME indeed. But it is hard to find and it really could use some documentation...

    Posted 07/20/2013
  • ivanhutchins
    1 of 5 2 of 5 3 of 5 4 of 5 5 of 5

    Sim-sim works excellent.

    Posted 06/01/2013
  • clifford_wolf
    1 of 5 2 of 5 3 of 5 4 of 5 5 of 5

    This project is AWESOME! Please present it more prominently so others can find it easier. At first I didn't try it because there was so little information here..

    Posted 05/23/2012
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Additional Project Details

User Interface

Qt

Programming Language

C++, Perl, VHDL/Verilog, Yacc

Registered

2006-07-12
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