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KPU-2.7a.zip 2014-10-12 749.8 kB 11 weekly downloads
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KPU-2.5b.zip 2014-06-28 771.6 kB 11 weekly downloads
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KPU-2.5a.zip 2014-06-26 832.0 kB 11 weekly downloads
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KPU-2.4i.zip 2014-06-21 843.1 kB 11 weekly downloads
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KPU-2.4h.zip 2014-06-19 841.8 kB 11 weekly downloads
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KPU-2.4g.zip 2014-06-15 838.3 kB 11 weekly downloads
KPU-2.4g.tgz 2014-06-15 793.5 kB 11 weekly downloads
KPU-2.4f.zip 2014-06-03 843.3 kB 11 weekly downloads
KPU-2.4f.tgz 2014-06-03 797.8 kB 11 weekly downloads
README 2014-06-03 7.6 kB 11 weekly downloads
KPU-2.4e.zip 2014-05-29 849.3 kB 11 weekly downloads
KPU-2.4e.tgz 2014-05-29 802.9 kB 11 weekly downloads
KPU-2.4d.zip 2014-05-26 849.1 kB 11 weekly downloads
KPU-2.4d.tgz 2014-05-26 802.9 kB 11 weekly downloads
KPU-2.4c.zip 2014-05-25 846.4 kB 11 weekly downloads
KPU-2.4c.tgz 2014-05-25 800.3 kB 11 weekly downloads
KPU-2.4b.zip 2014-05-24 850.8 kB 11 weekly downloads
KPU-2.4b.tgz 2014-05-24 803.7 kB 11 weekly downloads
KPU-2.4a.zip 2014-05-23 847.2 kB 11 weekly downloads
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KPU-2.3f.zip 2014-05-22 857.2 kB 22 weekly downloads
KPU-2.3f.tgz 2014-05-22 810.7 kB 11 weekly downloads
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KPU-2.3b.zip 2014-05-12 832.2 kB 22 weekly downloads
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KPU-2.3a.zip 2014-05-10 841.4 kB 11 weekly downloads
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KPU-2.2l.zip 2014-05-07 839.3 kB 11 weekly downloads
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KPU-2.2k.zip 2014-04-28 814.7 kB 11 weekly downloads
KPU-2.2k.tgz 2014-04-28 770.4 kB 11 weekly downloads
KPU-2.2j.zip 2014-04-28 797.2 kB 11 weekly downloads
KPU-2.2j.tgz 2014-04-28 756.2 kB 11 weekly downloads
KPU-2.2i.zip 2014-04-20 847.2 kB 11 weekly downloads
KPU-2.2i.tgz 2014-04-20 804.6 kB 11 weekly downloads
KPU-2.2h.zip 2014-04-17 835.3 kB 11 weekly downloads
KPU-2.2h.tgz 2014-04-17 796.2 kB 11 weekly downloads
KPU-2.2g.zip 2014-04-12 808.3 kB 0
KPU-2.2g.tgz 2014-04-12 766.8 kB 11 weekly downloads
KPU-2.2f.zip 2014-04-10 807.1 kB 11 weekly downloads
KPU-2.2f.tgz 2014-04-10 764.6 kB 11 weekly downloads
KPU-2.2e.zip 2014-04-09 817.9 kB 11 weekly downloads
KPU-2.2e.tgz 2014-04-09 774.9 kB 11 weekly downloads
KPU-2.2d.zip 2014-04-03 789.0 kB 0
KPU-2.2d.tgz 2014-04-03 746.9 kB 0
KPU-2.2c.zip 2014-03-31 781.6 kB 0
KPU-2.2c.tgz 2014-03-31 744.3 kB 0
KPU-2.2b.zip 2014-03-30 780.1 kB 11 weekly downloads
KPU-2.2b.tgz 2014-03-30 742.9 kB 0
KPU-2.2a.zip 2014-03-27 777.9 kB 0
KPU-2.2a.tgz 2014-03-27 740.7 kB 0
KPU-2.2.zip 2014-03-26 776.1 kB 11 weekly downloads
KPU-2.2.tgz 2014-03-26 739.1 kB 0
KPU-2.1j.zip 2014-03-25 775.9 kB 0
KPU-2.1j.tgz 2014-03-25 738.7 kB 0
KPU-2.1i.zip 2014-03-23 755.3 kB 0
KPU-2.1i.tgz 2014-03-23 718.6 kB 0
KPU-2.1h.zip 2014-03-23 750.6 kB 0
KPU-2.1h.tgz 2014-03-23 714.6 kB 0
KPU-2.1g.zip 2014-03-22 749.1 kB 11 weekly downloads
KPU-2.1g.tgz 2014-03-22 713.2 kB 0
KPU-2.1f.zip 2014-03-20 746.5 kB 11 weekly downloads
KPU-2.1f.tgz 2014-03-20 711.7 kB 0
KPU-2.1e.zip 2014-03-19 744.5 kB 11 weekly downloads
KPU-2.1e.tgz 2014-03-19 709.4 kB 11 weekly downloads
KPU-2.1d.zip 2014-03-17 739.9 kB 11 weekly downloads
KPU-2.1d.tgz 2014-03-17 703.8 kB 11 weekly downloads
KPU-2.1c.zip 2014-03-16 734.7 kB 11 weekly downloads
KPU-2.1c.tgz 2014-03-16 699.3 kB 11 weekly downloads
KPU-2.1b.tgz 2014-03-15 691.8 kB 11 weekly downloads
KPU-2.1b.zip 2014-03-15 726.1 kB 11 weekly downloads
KPU-2.1a.zip 2014-03-09 725.6 kB 11 weekly downloads
KPU-2.1a.tgz 2014-03-09 691.2 kB 11 weekly downloads
KPU-2.0c.zip 2014-03-07 722.4 kB 11 weekly downloads
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KPU-2.0b.zip 2014-03-07 723.1 kB 11 weekly downloads
KPU-2.0b.tgz 2014-03-07 688.5 kB 11 weekly downloads
KPU-2.0a.zip 2014-03-07 721.9 kB 11 weekly downloads
KPU-2.0a.tgz 2014-03-07 687.9 kB 11 weekly downloads
KPU-1.8a.zip 2014-03-02 704.3 kB 11 weekly downloads
KPU-1.8a.tgz 2014-03-02 672.4 kB 11 weekly downloads
KPU-1.8.zip 2014-02-24 687.3 kB 11 weekly downloads
KPU-1.8.tgz 2014-02-24 656.9 kB 11 weekly downloads
KPU-1.7b.zip 2014-02-23 686.8 kB 11 weekly downloads
KPU-1.7b.tgz 2014-02-23 655.8 kB 11 weekly downloads
KPU-1.7a.zip 2014-02-23 685.9 kB 11 weekly downloads
KPU-1.7a.tgz 2014-02-23 655.0 kB 11 weekly downloads
KPU-1.7.zip 2014-02-23 686.2 kB 11 weekly downloads
KPU-1.7.tgz 2014-02-23 655.5 kB 11 weekly downloads
KPU-1.6.zip 2014-02-23 683.6 kB 11 weekly downloads
KPU-1.6.tgz 2014-02-23 652.9 kB 11 weekly downloads
KPU-1.5.zip 2014-02-23 683.0 kB 11 weekly downloads
KPU-1.5.tgz 2014-02-23 652.3 kB 11 weekly downloads
KPU-1.4.zip 2014-02-23 683.1 kB 11 weekly downloads
KPU-1.4.tgz 2014-02-23 652.4 kB 11 weekly downloads
KPU-1.3.zip 2014-02-23 682.8 kB 11 weekly downloads
KPU-1.3.tgz 2014-02-23 652.0 kB 11 weekly downloads
KPU-1.2.zip 2014-02-23 682.6 kB 33 weekly downloads
KPU-1.2.tgz 2014-02-23 651.8 kB 33 weekly downloads
KPU-1a.1f.zip 2014-02-23 682.6 kB 33 weekly downloads
KPU-1a.1f.tgz 2014-02-23 651.4 kB 33 weekly downloads
KPU-1a.1e.zip 2014-02-23 682.6 kB 44 weekly downloads
KPU-1a.1e.tgz 2014-02-23 651.4 kB 33 weekly downloads
KPU-1a.1d.zip 2014-02-20 676.5 kB 33 weekly downloads
KPU-1a.1d.tgz 2014-02-20 646.8 kB 33 weekly downloads
KPU-1a.1b.zip 2014-02-20 674.8 kB 33 weekly downloads
KPU-1a.1b.tgz 2014-02-20 645.6 kB 33 weekly downloads
KPU-1a.1c.zip 2014-02-18 674.9 kB 33 weekly downloads
KPU-1a.1c.tgz 2014-02-18 645.9 kB 33 weekly downloads
KPU-1a.1.zip 2014-02-15 248.0 kB 11 weekly downloads
KPU-1a.1.tgz 2014-02-15 219.3 kB 11 weekly downloads
KPU-1a.1a.zip 2014-02-15 672.9 kB 11 weekly downloads
KPU-1a.1a.tgz 2014-02-15 630.8 kB 11 weekly downloads
KPU Good day and welcome. This is the README for the KPU code distribution. This is fundamentally a hack of the jMIPS code. jMIPS is a MIPS (that's a hardware CPU architecture) model in Java. Using jMIPS, one can run MIPS programs on any platform with Java support. KPU changes the basic jMIPS architecture to work on encrypted data and data addresses. In principle, it changes the arithmetic in the ALU inside the processor and that's about that. The code is a software model of a hardware architecture for prototyping purposes. Current uses of encryption are in 1) the ALU (alright); X) implementing bytewise instructions (OK - plan to eliminate bytewise instructions by compiling code that uses arithmetic on words instead); XXDONEXX 3) the Console printout routine (OK - that's just a convenience so that one doesn't go cross-eyed looking the output); 4) debugging routines (OK); X) in the Registers unit to set register $0 to the value of encrypted zero (OK - the compiler can fill it, and if necessary we can implement a command to lock the register afterwards, since it's supposed to be a sink as well as a source); XXDONEXX X) in Memory, to find the right RAM unit to address and to implement some bytewise accesses (OK on the bytewise accesses, since we should get rid of them at compile time, not OK on the use for selecting RAM). That's more or less all gone now, but the solution isn't definitive yet, so it might come in and out still. XXDONEXX MORE ON THE ORIGINAL jMIPS CODE Primarily for helping undergraduate students to understand their Computer Systems Architecture courses, which traditionally use a RISC architecture, usually MIPS, as the basis. The idea was that this Java code be (a) simple, (b) understandable, (c) provide a model of a CPU both in the sense of the runtime and structure that is accessible to students. The jMIPS code provides objects that individually emulate the functional parts of a CPU - the ALU, registers, memory, I/O bus, etc. There's a CPUx.java (for x=1 to 5, representing consecutively more sophisticated models) which builds the CPU out of those parts, connects them together, and supplies the run() method. The main() code calls the constructor for CPUx, sets its stack pointer and program counter, and calls the run() method. Who could fail to understand that! It works. It runs MIPS executable files (ELF format). I implemented almost all the 32-bit MIPS ISA. The evidence from those students who looked at the jMIPS code as part of their undergraduate course is that it was a help to them, and made things clear that might otherwise have remained clouded. For example, it is clear after looking at the code that you CAN both write to a register and read from it at the same time. For some reason confused students tend to think that one can't both read and write to a register simultaneously. One CAN. The read sees the previous value while the write puts in the next value. The changeover happens on the clock pulse edge. The originally five, now seven, different pipeline models were intended to be each successively faster on the test machine code files. The default output from the simulator is instruction by instruction timing data. The jMIPS code came with a pile of HTML documention which makes up a guided tour through the different CPU model architectures. You will find it in the doc/html subdirectory. COPYRIGHT The primary copyright (C) 2009/2010 author is Peter T. Breuer. CONTACT ptb@cs.bham.ac.uk ptb@ieee.org ptb@inv.it.uc3m.es Peter T. Breuer Dept. Comp. Sci. University of Birmingham Edgbaston B15 2TT Birmingham, UK LICENCE The program is released under the GPL v3 licence. The appropriate rubric that I should quote in that respect is: This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. Indeed, you'll find the GPLv3 in the COPYING file alongside this README in the same directory. If it isn't there, please follow the URL quoted above and retrieve it. My personal executive take on the GPLv3 is that you are free to use and modify the source or any code compiled or otherwise derived from it for your own purposes. You are also permitted to pass on the code or your derivation by most means including distribution, sale and resale, but you must pass on this or your derived product under THIS licence. There are two major implications: firstly, when you pass on a binary, you must also provide the receiver with a way to get hold of the source code to the binary. Secondly, the receiver also becomes bound by this licence, and that's the well-known "viral" aspect. What happens if you don't obey? Then you are in breach of the licence to the code so you lose the licence's protection and you are now likely in breach of copyright, with the subsequent statutory penalities and horrible remedies that may be applicable. You may add extra licence conditions as you pass on the code, provided you do not contradict the original GPLv3 licence. That's hard to do, since GPLv3 opens holes in copyright restrictions for you, and the way GPLv3 is crafted, you would contradict it by closing those holes. There are known compatible licences, however. See the GPL URL. About the only thing you could do to get hold of the code under a really different licence is to ask me, as original author, to re-release my code to you under that licence instead, and take it from there. That's my take. For the exact words of advice setting out the understanding you should receive, see the GPLv3 text itself! You won't go far wrong if you understand that GPLv3 is about maintaining the freedom of the receivers of compiled or derived code to change and modify what they receive as they wish. COMPILATION Type "make". Yes, there's a Makefile. You need a unix-style "make" program. What it does for you is: javac CPU/Cpu1.java ... javac CPU/Cpu5.java so if your java bytecode compiler is not called "javac", you may need to make some changes. That should build all the CPU/*.class files. If you have a native code compiler, you may waht to use that instead. RUN Run the compiled bytecode in a Java Virtual Machine as follows: java CPU/Cpu1 ../misc/hello_mips32 You'll likely want a "-q" as a command line option in order to stop the extra noise that's emitted by default: java CPU/Cpu1 -q ../misc/hello_mips32 CPU5 needs an interrupt handler too: java CPU/Cpu5 -q ../misc/hello_mips32 ../misc/handler_mips32 And CPU6 and CPU7 need a TLB fault handler: java CPU/Cpu6 -q ../misc/hello_mips32 ../misc/handler_mips32 c/handler BUGS etc. If you find something wrong, fix it :0). Or just talk to me about it. I'll happily take patches and your name will go into the credits. Peter T. Breuer, April 2010 ptb@cs.bham.ac.uk
Source: README, updated 2014-06-03