Re: [Valgrind-users] cache model used in cachegrind

[Wan M. F. W. I. <wan...@mc...>]

Hi,
I think it's necessary to have an approximate model for each processor (ARM,
PowerPC, etc) since their cache models are different. It might be a good
idea if we can have a better flexibility to use the tool ( eg: the choice of
replacement policy). From what I see, eventhough the tool itself  has been
ported to arm, but the cache model used is still x86's.

Kind regards,
Fairuz

On Fri, Feb 18, 2011 at 8:14 PM, Josef Weidendorfer <
Jos...@gm...> wrote:

> On Friday 18 February 2011, Wan Mohd Fairuz Wan Ismail wrote:
> > Hi,
> > Do cachegrind use the same cache model for different processors? (eg.
> x86,
> > armv7-a8, armv7-a9, etc).
>
> Yes. 2 levels (L1 separate for I/D, the other unified), inclusive,
> synchronous, LRU replacement.
> Only parameters are adapted to current processor: size, line size,
> associatvity.
> If a processor has 3 levels, parameters of L1 and L3 are actually used.
>
> This model actually is most near to Intel processors, but it always was
> just
> an approximation. Especially it is not simulating the AMD processor
> exclusive
> caches (where L2/L3 are victim caches).
>
> The idea of this simple model is not to be as near as possible to real
> hardware,
> but to highlight common problems of an application regarding cache
> behavior, such
> that the code afterwards would run faster on every architecture using
> caches.
>
> Do you see a need for more exact models?
>
> Josef
>
>
> >
> > Thanks,
> > Kind regards,
> >
>
>
>


-- 
Wan Mohd Fairuz WAN ISMAIL
Masters in Electronics Engineering,
Majoring in Embedded System Engineering,
Polytech Nice Sophia Antipolis, FRANCE.

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