[Valgrind-users] Cachegrind - hardware prefetching.

[Konstantinos K. <K.K...@sm...>]

Hi,

I run cachegrind on a AMD Athlon 4200+ 64x2 system and get these
results:

 Cachegrind, an I1/D1/L2 cache profiler.
 Copyright (C) 2002-2006, and GNU GPL'd, by Nicholas Nethercote et al.
 Using LibVEX rev 1658, a library for dynamic binary translation.
 Copyright (C) 2004-2006, and GNU GPL'd, by OpenWorks LLP.
 Using valgrind-3.2.1, a dynamic binary instrumentation framework.
 Copyright (C) 2000-2006, and GNU GPL'd, by Julian Seward et al.
 For more details, rerun with: -v
 
 
 I   refs:      3,641,862,524
 I1  misses:            1,050
 L2i misses:            1,041
 I1  miss rate:          0.00%
 L2i miss rate:          0.00%
 
 D   refs:      1,355,109,542  (839,732,151 rd + 515,377,391 wr)
 D1  misses:        2,299,014  (  1,426,783 rd +     872,231 wr)
 L2d misses:        1,603,411  (    812,790 rd +     790,621 wr)
 D1  miss rate:           0.1% (        0.1%   +         0.1%  )
 L2d miss rate:           0.1% (        0.0%   +         0.1%  )
 
 L2 refs:           2,300,064  (  1,427,833 rd +     872,231 wr)
 L2 misses:         1,604,452  (    813,831 rd +     790,621 wr)
 L2 miss rate:            0.0% (        0.0%   +         0.1%  )

-Are these results valid? The miss rates should be must higher, if they
are calculated as references/misses. 
-Does cachegrind simulate hardware prefetching mechanisms. If yes, does
it adjust its functionality to the characteristics of the specific
processor? 

Thanks.