From: Wojciech Z. <wz...@gm...> - 2015-05-17 13:34:26
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Hi, DISCLAIMER: The procedure described below may be risky, as the source BSDL file had to be modified. There is a risk, that removed sections contain information important for safe control of the FPGA via JTAG. If you are going to use the described procedure, you do it ON YOUR OWN RISK! I had to use UrJTAG with our boards based on Kintex 7 xc7K325t-ffg900 chip. Unfortunately this chip was not supported by UrJTAG. I tried to generate the "jtag" file from the xc7k325t_ffg900.bsd provided with Xilinx Vivado, but it resulted in error: bsdl2jtag xc7k325t_ffg900.bsd xc7k325t_ffg900 error: -E- error: In Package STD_1149_6_2003, Line 755, Error in User-Defined Package declarations. error: -E- error: BSDL file 'xc7k325t_ffg900.bsd' contains errors in VHDL stage, stopping error: system error: Success Cannot open file STD_1149_6_2003 or /usr/local/wzab/urjtag/share/urjtag/bsdl/STD_1149_6_2003 Basing on discussion: https://sourceforge.net/p/urjtag/mailman/message/30062425/ I have removed the line 755: use STD_1149_6_2003.all; And then, retrying the conversion, I had to remove yet some sections: 1. The one starting from (near to line 1407): > attribute PORT_GROUPING of XC7K325T_FFG900 : entity is > "DIFFERENTIAL_VOLTAGE (" & > "(MGTXRXP0_115, MGTXRXN0_115), " & > [...] 2. The one starting from (near to line 3193): > attribute AIO_COMPONENT_CONFORMANCE of XC7K325T_FFG900 : entity is > "STD_1149_6_2003"; > > attribute AIO_EXTEST_Pulse_Execution of XC7K325T_FFG900 : entity is > "Wait_Duration TCK 15"; > > attribute AIO_EXTEST_Train_Execution of XC7K325T_FFG900 : entity is > "train 30, maximum_time 120.0e-6"; > > attribute AIO_Pin_Behavior of XC7K325T_FFG900 : entity is > "MGTXRXP0_115 : LP_time=22.5e-9 HP_time=45.0e-9; " & > "MGTXRXP0_116 : LP_time=22.5e-9 HP_time=45.0e-9; " & > [...] Afterwards the file converted cleanly, and UrJTAG was able to recognize the chip. Of course there is a risk, that removal of certain incompatible sections may result in improper control of chip via JTAG, which may lead to destruction of the chip. I don't fully understand meaning of removed sections, so I do not provide any warranty, that the described procedure is safe. If you are going to use it, you do it on your own risk. -- With best regards, Wojtek Wojciech M. Zabołotny My GPG/PGP keys: standard: 8192R/FE58A848 (0720 9430 85DB 7CCD F4C5 5F1E 5107 91FB FE58 A848) confidential: 16384R/C76D2FB0 (C4E7 9597 CF22 7B5D 28BF 4656 FED7 A63F C76D 2FB0) |