[sigrok-devel] support for new open hardware and open software logic analyzer [hsa-tple], but some more help required

[Matthias W. <mat...@gm...>]

Hi all,

as I already told you about we have been developing an open source and
open hardware logic analyzer at Hochschule Augsburg during this winter
semester. We have implemented the API and the protocol on the PC side.

It finally became a serial protocol (virtual serial via USB, sorry guys)
due to a lack of time. But as (almost) everything seems to work now feel
free to contribute and help implement another USB protocol.

A short abstract:
* 8 channels
  (24 channels planned, but had not enough logic elements of the CPLD)
* [currently fixed] sample rate of 6.25 MSamples/s
  (this correspons to a resolution of 160 ns)
* memory for up to 262'144 samples
  the sample storage format is 4 bytes / 32 bit:
  - 16 bit timestamp
    (we only store new samples and therefore have kind of internal VCD)
  - 8 bit data
  - 8 bit status
* controllable via USB
  - includes meausurement as well as
  - microcontroller firmware update and
  - CPLD firmware update via uC JTAG bridge
* open hardware and open software
* fully homebrew at Hochschule Augsburg
* low-cost, standard components
* no external power supply required (USB-powered)

Hardware components:
* CPLD: Altera Max II with 240 logic elements
  (programmed in VHDL)
* microcontroller: Atmel ATmega32u4
  (programmed in C)
* 2x RAM organised as 256K*16
* I/O drivers supporting 5V and 3V as input voltage

If you agree I'll put this information in the wiki also. Also with
further hyperlinks (our internal wiki is not yet publically available,
but hopefully will be soon) and pictures.

Unfortnately it isn't running 100% yet, please help us getting it done.
We're facing some problems with the session bus. For the sake of clarity
I'll let you know in another mail.

Enjoy your weekend,
Matthias