From: Bert S. <ber...@es...> - 2003-07-13 21:33:52
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/*-----------------------------------------------------------------------= ---- ; Copyright (C) 2003 CYGNAL INTEGRATED PRODUCTS, INC. ; All rights reserved. ; ; ; FILE NAME : C8051F320.H ; TARGET MCUs : C8051F320, 'F321, 'F322, 'F323 ; DESCRIPTION : Register/bit definitions for the C8051F32x product = family. ; ; REVISION 1.3 ; -- added EIE2, EIP1, EIP2, EMI0CN, Bert Schiettecatte ; REVISION 1.2 ; -- added SPI0CFG, SPI0CKR, and SPI0DAT (left SPICFG, SPICKR, and = SPIDAT as-is) ; REVISION 1.1 ; ;------------------------------------------------------------------------= ---*/ /* Modified by Josh Stone to support the SDCC (v2.3.5) compiler */ /* BYTE Registers */ sfr at 0x80 P0; /* PORT 0 = */ sfr at 0x81 SP; /* STACK POINTER = */ sfr at 0x82 DPL; /* DATA POINTER - LOW BYTE = */ sfr at 0x83 DPH; /* DATA POINTER - HIGH BYTE = */ sfr at 0x87 PCON; /* POWER CONTROL = */ sfr at 0x88 TCON; /* TIMER CONTROL = */ sfr at 0x89 TMOD; /* TIMER MODE = */ sfr at 0x8A TL0; /* TIMER 0 - LOW BYTE = */ sfr at 0x8B TL1; /* TIMER 1 - LOW BYTE = */ sfr at 0x8C TH0; /* TIMER 0 - HIGH BYTE = */ sfr at 0x8D TH1; /* TIMER 1 - HIGH BYTE = */ sfr at 0x8E CKCON; /* CLOCK CONTROL = */ sfr at 0x8F PSCTL; /* PROGRAM STORE R/W CONTROL = */ sfr at 0x90 P1; /* PORT 1 = */ sfr at 0x91 TMR3CN; /* TIMER 3 CONTROL = */ sfr at 0x92 TMR3RLL; /* TIMER 3 RELOAD LOW = */ sfr at 0x93 TMR3RLH; /* TIMER 3 RELOAD HIGH = */ sfr at 0x94 TMR3L; /* TIMER 3 LOW BYTE = */ sfr at 0x95 TMR3H; /* TIMER 3 HIGH BYTE = */ sfr at 0x96 USB0ADR; /* USB0 ADDRESS PORT = */ sfr at 0x97 USB0DAT; /* USB0 DATA PORT = */ sfr at 0x98 SCON0; /* SERIAL PORT 0 CONTROL = */ sfr at 0x99 SBUF0; /* SERIAL PORT 0 BUFFER = */ sfr at 0x9A CPT1CN; /* COMPARATOR 1 CONTROL = */ sfr at 0x9B CPT0CN; /* COMPARATOR 0 CONTROL = */ sfr at 0x9C CPT1MD; /* COMPARATOR 1 MODE = */ sfr at 0x9D CPT0MD; /* COMPARATOR 0 MODE = */ sfr at 0x9E CPT1MX; /* COMPARATOR 1 MUX = */ sfr at 0x9F CPT0MX; /* COMPARATOR 0 MUX = */ sfr at 0xA0 P2; /* PORT 2 = */ sfr at 0xA1 SPICFG; /* SPIO CONFIGURATION = */ sfr at 0xA1 SPIOCFG; /* SPIO CONFIGURATION = */ sfr at 0xA2 SPICKR; /* SPIO CLOCK CONFIGURATION = */ sfr at 0xA2 SPIOCKR; /* SPIO CLOCK CONFIGURATION = */ sfr at 0xA3 SPIDAT; /* SPIO DATA = */ sfr at 0xA3 SPIODAT; /* SPIO DATA = */ sfr at 0xA4 P0MDOUT; /* PORT 0 OUTPUT MODE = */ sfr at 0xA5 P1MDOUT; /* PORT 1 OUTPUT MODE = */ sfr at 0xA6 P2MDOUT; /* PORT 2 OUTPUT MODE = */ sfr at 0xA7 P3MDOUT; /* PORT 3 OUTPUT MODE = */ sfr at 0xA8 IE; /* INTERRUPT ENABLE = */ sfr at 0xA9 CLKSEL; /* CLOCK SOURCE SELECT = */ sfr at 0xAA EMI0CN; /* EXTERNAL MEMORY INTERFACE CONTROL = */ sfr at 0xB0 P3; /* PORT 3 = */ sfr at 0xB1 OSCXCN; /* EXTERNAL OSCILLATOR CONTROL = */ sfr at 0xB2 OSCICN; /* INTERNAL OSCILLATOR CONTROL = */ sfr at 0xB3 OSCICL; /* INTERNAL OSCILLATOR CALIBRATION = */ sfr at 0xB6 FLSCL; /* FLASH SCALE = */ sfr at 0xB7 FLKEY; /* FLASH LOCK & KEY = */ sfr at 0xB8 IP; /* INTERRUPT PRIORITY = */ sfr at 0xB9 CLKMUL; /* CLOCK MULTIPLIER CONTROL = */ sfr at 0xBA AMX0N; /* ADC0 MUX NEGATIVE CHANNEL SELECTION = */ sfr at 0xBB AMX0P; /* ADC0 MUX POSITIVE CHANNEL SELECTION = */ sfr at 0xBC ADC0CF; /* ADC0 CONFIGURATION = */ sfr at 0xBD ADC0L; /* ADC0 DATA LOW = */ sfr at 0xBE ADC0H; /* ADC0 DATA HIGH = */ sfr at 0xC0 SMB0CN; /* SMBUS CONTROL = */ sfr at 0xC1 SMB0CF; /* SMBUS CONFIGURATION = */ sfr at 0xC2 SMB0DAT; /* SMBUS DATA = */ sfr at 0xC3 ADC0GTL; /* ADC0 GREATER-THAN LOW = */ sfr at 0xC4 ADC0GTH; /* ADC0 GREATER-THAN HIGH = */ sfr at 0xC5 ADC0LTL; /* ADC0 LESS-THAN LOW = */ sfr at 0xC6 ADC0LTH; /* ADC0 LESS-THAN HIGH = */ sfr at 0xC8 TMR2CN; /* TIMER 2 CONTROL = */ sfr at 0xC9 REG0CN; /* REGULATOR CONTROl = */ sfr at 0xCA TMR2RLL; /* TIMER 2 RELOAD LOW = */ sfr at 0xCB TMR2RLH; /* TIMER 2 RELOAD HIGH = */ sfr at 0xCC TMR2L; /* TIMER 2 LOW BYTE = */ sfr at 0xCD TMR2H; /* TIMER 2 HIGH BYTE = */ sfr at 0xD0 PSW; /* PROGRAM STATUS WORD = */ sfr at 0xD1 REF0CN; /* VOLTAGE REFERENCE 0 CONTROL = */ sfr at 0xD4 P0SKIP; /* PORT 0 CROSSBAR SKIP = */ sfr at 0xD5 P1SKIP; /* PORT 1 CROSSBAR SKIP = */ sfr at 0xD6 P2SKIP; /* PORT 2 CROSSBAR SKIP = */ sfr at 0xD7 USB0XCN; /* USB0 TRANCEIVER CONTROL = */ sfr at 0xD8 PCA0CN; /* PCA0 CONTROL = */ sfr at 0xD9 PCA0MD; /* PCA0 MODE = */ sfr at 0xDA PCA0CPM0; /* PCA0 MODULE 0 MODE = */ sfr at 0xDB PCA0CPM1; /* PCA0 MODULE 1 MODE = */ sfr at 0xDC PCA0CPM2; /* PCA0 MODULE 2 MODE = */ sfr at 0xDD PCA0CPM3; /* PCA0 MODULE 3 MODE = */ sfr at 0xDE PCA0CPM4; /* PCA0 MODULE 4 MODE = */ sfr at 0xE0 ACC; /* ACCUMULATOR = */ sfr at 0xE1 XBR0; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 = */ sfr at 0xE2 XBR1; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 = */ sfr at 0xE4 IT01CF; /* INT0/INT1 CONFIGURATION = */ sfr at 0xE6 EIE1; /* EXTENDED INTERRUPT ENABLE 1 = */ sfr at 0xE7 EIE2; /* EXTENDED INTERRUPT ENABLE 2 = */ sfr at 0xE8 ADC0CN; /* ADC 0 CONTROL = */ sfr at 0xE9 PCA0CPL1; /* PCA0 MODULE 1 CAPTURE/COMPARE REGISTER LOW = BYTE */ sfr at 0xEA PCA0CPH1; /* PCA0 MODULE 1 CAPTURE/COMPARE REGISTER HIGH = BYTE */ sfr at 0xEB PCA0CPL2; /* PCA0 MODULE 2 CAPTURE/COMPARE REGISTER LOW = BYTE */ sfr at 0xEC PCA0CPH2; /* PCA0 MODULE 2 CAPTURE/COMPARE REGISTER HIGH = BYTE */ sfr at 0xED PCA0CPL3; /* PCA0 MODULE 3 CAPTURE/COMPARE REGISTER LOW = BYTE */ sfr at 0xEE PCA0CPH3; /* PCA0 MODULE 3 CAPTURE/COMPARE REGISTER HIGH = BYTE */ sfr at 0xEF RSTSRC; /* RESET SOURCE = */ sfr at 0xF0 B; /* B REGISTER = */ sfr at 0xF1 P0MDIN; /* PORT 0 INPUT MODE REGISTER = */ sfr at 0xF2 P1MDIN; /* PORT 1 INPUT MODE REGISTER = */ sfr at 0xF3 P2MDIN; /* PORT 2 INPUT MODE REGISTER = */ sfr at 0xF4 P3MDIN; /* PORT 3 INPUT MODE REGISTER = */ sfr at 0xF6 EIP1; /* EXTENDED INTERRUPT PRIORITY 1 = */ sfr at 0xF7 EIP2; /* EXTENDED INTERRUPT PRIORITY 2 = */ sfr at 0xF8 SPI0CN; /* SPI0 CONTROL = */ sfr at 0xF9 PCA0L; /* PCA0 COUNTER REGISTER LOW BYTE = */ sfr at 0xFA PCA0H; /* PCA0 COUNTER REGISTER HIGH BYTE = */ sfr at 0xFB PCA0CPL0; /* PCA MODULE 0 CAPTURE/COMPARE REGISTER LOW = BYTE */ sfr at 0xFC PCA0CPH0; /* PCA MODULE 0 CAPTURE/COMPARE REGISTER HIGH = BYTE */ sfr at 0xFD PCA0CPL4; /* PCA MODULE 4 CAPTURE/COMPARE REGISTER LOW = BYTE */ sfr at 0xFE PCA0CPH4; /* PCA MODULE 4 CAPTURE/COMPARE REGISTER HIGH = BYTE */ sfr at 0xFF VDM0CN; /* VDD MONITOR CONTROL = */ /* BIT Registers */ #define TCON 0x88 sbit at TCON ^ 0 IT0; /* EXT INTERRUPT 0 TYPE = */ sbit at TCON ^ 1 IE0; /* EXT INTERRUPT 0 EDGE FLAG = */ sbit at TCON ^ 2 IT1; /* EXT INTERRUPT 1 TYPE = */ sbit at TCON ^ 3 IE1; /* EXT INTERRUPT 1 EDGE FLAG = */ sbit at TCON ^ 4 TR0; /* TIMER 0 ON/OFF CONTROL = */ sbit at TCON ^ 5 TF0; /* TIMER 0 OVERFLOW FLAG = */ sbit at TCON ^ 6 TR1; /* TIMER 1 ON/OFF CONTROL = */ sbit at TCON ^ 7 TF1; /* TIMER 1 OVERFLOW FLAG = */ #undef TCON #define SCON0 0x98 sbit at SCON0 ^ 0 RI0; /* RECEIVE INTERRUPT FLAG = */ sbit at SCON0 ^ 1 TI0; /* TRANSMIT INTERRUPT FLAG = */ sbit at SCON0 ^ 2 RB80; /* RECEIVE BIT 8 = */ sbit at SCON0 ^ 3 TB80; /* TRANSMIT BIT 8 = */ sbit at SCON0 ^ 4 REN0; /* RECEIVE ENABLE = */ sbit at SCON0 ^ 5 MCE0; /* MULTIPROCESSOR COMMUNICATION ENABLE = */ sbit at SCON0 ^ 7 S0MODE; /* SERIAL MODE CONTROL BIT 0 = */ #undef SCON0 #define IE 0xA8 sbit at IE ^ 0 EX0; /* EXTERNAL INTERRUPT 0 ENABLE = */ sbit at IE ^ 1 ET0; /* TIMER 0 INTERRUPT ENABLE = */ sbit at IE ^ 2 EX1; /* EXTERNAL INTERRUPT 1 ENABLE = */ sbit at IE ^ 3 ET1; /* TIMER 1 INTERRUPT ENABLE = */ sbit at IE ^ 4 ES0; /* UART0 INTERRUPT ENABLE = */ sbit at IE ^ 5 ET2; /* TIMER 2 INTERRUPT ENABLE = */ sbit at IE ^ 7 EA; /* GLOBAL INTERRUPT ENABLE = */ #undef IE #define IP 0xB8 sbit at IP ^ 0 PX0; /* EXTERNAL INTERRUPT 0 PRIORITY = */ sbit at IP ^ 1 PT0; /* TIMER 0 PRIORITY = */ sbit at IP ^ 2 PX1; /* EXTERNAL INTERRUPT 1 PRIORITY = */ sbit at IP ^ 3 PT1; /* TIMER 1 PRIORITY = */ sbit at IP ^ 4 PS0; /* UART0 PRIORITY = */ sbit at IP ^ 5 PT2; /* TIMER 2 PRIORITY = */ #undef IP #define SMB0CN 0xC0 sbit at SMB0CN ^ 0 SI; /* SMBUS0 INTERRUPT FLAG = */ sbit at SMB0CN ^ 1 ACK; /* ACKNOWLEDGE FLAG = */ sbit at SMB0CN ^ 2 ARBLOST; /* ARBITRATION LOST INDICATOR = */ sbit at SMB0CN ^ 3 ACKRQ; /* ACKNOWLEDGE REQUEST = */ sbit at SMB0CN ^ 4 STO; /* STOP FLAG = */ sbit at SMB0CN ^ 5 STA; /* START FLAG = */ sbit at SMB0CN ^ 6 TXMODE; /* TRANSMIT MODE INDICATOR = */ sbit at SMB0CN ^ 7 MASTER; /* MASTER/SLAVE INDICATOR = */ #undef SMB0CN #define TMR2CN 0xC8 sbit at TMR2CN ^ 0 T2XCLK; /* TIMER 2 EXTERNAL CLOCK SELECT = */ sbit at TMR2CN ^ 2 TR2; /* TIMER 2 ON/OFF CONTROL = */ sbit at TMR2CN ^ 3 T2SPLIT; /* TIMER 2 SPLIT MODE ENABLE = */ sbit at TMR2CN ^ 5 TF2LEN; /* TIMER 2 LOW BYTE INTERRUPT ENABLE = */ sbit at TMR2CN ^ 6 TF2L; /* TIMER 2 LOW BYTE OVERFLOW FLAG = */ sbit at TMR2CN ^ 7 TF2H; /* TIMER 2 HIGH BYTE OVERFLOW FLAG = */ #undef TMR2CN #define PSW 0xD0 sbit at PSW ^ 0 P; /* ACCUMULATOR PARITY FLAG = */ sbit at PSW ^ 1 F1; /* USER FLAG 1 = */ sbit at PSW ^ 2 OV; /* OVERFLOW FLAG = */ sbit at PSW ^ 3 RS0; /* REGISTER BANK SELECT 0 = */ sbit at PSW ^ 4 RS1; /* REGISTER BANK SELECT 1 = */ sbit at PSW ^ 5 F0; /* USER FLAG 0 = */ sbit at PSW ^ 6 AC; /* AUXILIARY CARRY FLAG = */ sbit at PSW ^ 7 CY; /* CARRY FLAG = */ #undef PSW #define PCA0CN 0xD8 sbit at PCA0CN ^ 0 CCF0; /* PCA0 MODULE 0 CAPTURE/COMPARE FLAG = */ sbit at PCA0CN ^ 1 CCF1; /* PCA0 MODULE 1 CAPTURE/COMPARE FLAG = */ sbit at PCA0CN ^ 2 CCF2; /* PCA0 MODULE 2 CAPTURE/COMPARE FLAG = */ sbit at PCA0CN ^ 3 CCF3; /* PCA0 MODULE 3 CAPTURE/COMPARE FLAG = */ sbit at PCA0CN ^ 4 CCF4; /* PCA0 MODULE 4 CAPTURE/COMPARE FLAG = */ sbit at PCA0CN ^ 6 CR; /* PCA0 COUNTER RUN CONTROL = */ sbit at PCA0CN ^ 7 CF; /* PCA0 COUNTER OVERFLOW FLAG = */ #undef PCA0CN #define ADC0CN 0xE8 sbit at ADC0CN ^ 0 AD0CM0; /* ADC0 CONVERSION MODE SELECT 0 = */ sbit at ADC0CN ^ 1 AD0CM1; /* ADC0 CONVERSION MODE SELECT 1 = */ sbit at ADC0CN ^ 2 AD0CM2; /* ADC0 CONVERSION MODE SELECT 2 = */ sbit at ADC0CN ^ 3 AD0WINT; /* ADC0 WINDOW COMPARE INTERRUPT FLAG = */ sbit at ADC0CN ^ 4 AD0BUSY; /* ADC0 BUSY FLAG = */ sbit at ADC0CN ^ 5 AD0INT; /* ADC0 CONVERISION COMPLETE INTERRUPT FLAG = */ sbit at ADC0CN ^ 6 AD0TM; /* ADC0 TRACK MODE = */ sbit at ADC0CN ^ 7 AD0EN; /* ADC0 ENABLE = */ #undef ADC0CN #define SPI0CN 0xF8 sbit at SPI0CN ^ 7 SPIF; /* SPI 0 INTERRUPT FLAG = */ sbit at SPI0CN ^ 6 WCOL; /* SPI 0 WRITE COLLISION FLAG = */ sbit at SPI0CN ^ 5 MODF; /* SPI 0 MODE FAULT FLAG = */ sbit at SPI0CN ^ 4 RXOVRN; /* SPI 0 RX OVERRUN FLAG = */ sbit at SPI0CN ^ 3 TXBSY; /* SPI 0 SLAVE SELECT MODE 1 = */ sbit at SPI0CN ^ 2 SLVSEL; /* SPI 0 SLAVE SELECT MODE 0 = */ sbit at SPI0CN ^ 1 TXBMT; /* SPI 0 TRANSMIT BUFFER EMPTY = */ sbit at SPI0CN ^ 0 SPIEN; /* SPI 0 SPI ENABLE = */ #undef SPI0CN |
From: Josh S. <jo...@4s...> - 2003-07-14 15:37:05
Attachments:
c8051F320.h
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Hi Bert, I wasn't able to get SDCC working properly in the Cygnal IDE. Even using the batch-file support failed when I tried. But, I didn't really try hard, so it still may be possible. If you ask me, the IDE isn't that great anyway for editing the source code. I will admit though that the debugging interface is pretty cool. If you add "--debug" to your SDCC command line, it will create the OMF file (the file with no extension) that you can use with Cygnal's debugger. As for the header file, I'm suprised that the "official" Cygnal header file left stuff out, but there it is. You inspired me to look if they left anything else out as well. It seems that you found all of the sfr's, but there were a few sbit's I found in the datasheet that were still undefined. So, I added those and attached the file for your use. Regards, Josh Stone -----Original Message----- From: sdc...@li... [mailto:sdc...@li...]On Behalf Of Bert Schiettecatte Sent: Sunday, July 13, 2003 3:33 PM To: sdc...@li... Subject: [Sdcc-user] Cygnal IDE and SDCC Hi all, I’m thinking of setting up SDCC in the Cygnal IDE to be able to use all the nice benefits of the IDE like debugging etc, with SDCC. The IDE has support for different tool chains, you can choose the path to the assembler, compiler and linker executables and add extra command line options. Does anyone on this list know what to pass to the IDE to compile, assemble and link with SDCC in separate steps? I’m also attaching a revised version of the C8051F320 include file for whoever is interested. I’ve added a few SFRs. Thanks, bert --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.500 / Virus Database: 298 - Release Date: 10/07/2003 |
From: Bert S. <ber...@es...> - 2003-07-14 17:57:02
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Hi Josh, Thanks a lot for the updated header file! I'll let you know in case I get the Cygnal IDE working with SDCC. Bert Schiettecatte --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.500 / Virus Database: 298 - Release Date: 10/07/2003 |
From: Bert S. <ber...@es...> - 2003-07-14 18:57:12
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Hi Josh, I tried porting Cygnal's USB_INT example to SDCC but no luck. I finally managed to make it all compile using your Makefile.dat and I flashed the development Board using FLASHProg. Unfortunately the USB device is now no longer recognized by Windows...! Do you have any idea what's happening? This is of course related to my post about the curly braces. Thanks, Bert Schiettecatte --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.500 / Virus Database: 298 - Release Date: 10/07/2003 |
From: Josh S. <jo...@4s...> - 2003-07-14 19:53:07
Attachments:
USB_INT.zip
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Sorry, it seems I forgot to mention the little idiosyncrasies I ran into in porting the project. I have included a zip with a working version so you don't have to go through the same hassle. But it may help you to understand what was done, so I'll try to explain. If you got it to compile, then you must have fixed the curly braces, so I'll move on. The next (and last, I think) issue for you to resolve is the "endian"-ness of the compilers and protocol. The USB protocol is little-endian, SDCC is little-endian, and Keil is big-endian. If you need an explanation of endian, see this link: http://www.webopedia.com/TERM/B/big_endian.html What this means is that the developers who wrote the example hard-coded a few places where it flips the bytes. For example, in USB_Descriptor.h, you have the line: {0xC410}, // idVendor Cygnal's VID is actually 0x10C4 - but the developer flipped it since Keil and USB interpret int's differently. USB and SDCC, however, are both little-endian, so the correction goes: {0x10C4}, // idVendor You'll also see a MSB and LSB next to the definition of WORD, which I now changed to this: // WORD type definition, for SDCC Compiler #ifndef _WORD_DEF_ #define _WORD_DEF_ typedef union {unsigned int i; unsigned char c[2];} WORD; #define LSB 0 #define MSB 1 #endif /* _WORD_DEF_ */ Going through the code, I also found a few places where they were manually flipping bytes on transmissions to/from the host... most of these code sections I removed. I realize this is a pretty brief description of the changes needed, but if you use the version I have attached, you should be ready to go. I made sure that this version does compile correctly, and when you download it to the board, you should be able to use Cygnal's USBTest.exe to talk to the board. Hope this helps, Josh Stone PS - Incidentally, this version of my code was actually shortly after I had started modifying it for my own purposes. All of the functionality is still the same as the original, but you'll notice that the headers at the top of each file are now listed with my name. Sorry if this is an inconvenience - feel free to change that... :-D -----Original Message----- From: sdc...@li... [mailto:sdc...@li...]On Behalf Of Bert Schiettecatte Sent: Monday, July 14, 2003 12:57 PM To: sdc...@li... Subject: RE: [Sdcc-user] Cygnal IDE and SDCC Hi Josh, I tried porting Cygnal's USB_INT example to SDCC but no luck. I finally managed to make it all compile using your Makefile.dat and I flashed the development Board using FLASHProg. Unfortunately the USB device is now no longer recognized by Windows...! Do you have any idea what's happening? This is of course related to my post about the curly braces. Thanks, Bert Schiettecatte --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.500 / Virus Database: 298 - Release Date: 10/07/2003 ------------------------------------------------------- This SF.Net email sponsored by: Parasoft Error proof Web apps, automate testing & more. Download & eval WebKing and get a free book. www.parasoft.com/bulletproofapps1 _______________________________________________ Sdcc-user mailing list Sdc...@li... https://lists.sourceforge.net/lists/listinfo/sdcc-user |