[Ppcboot-users] Decrementer Problem

[Manuel T. Dall'O. <mt...@tc...>]

When an interrupt takes place. For example (DECREMENTER Interrupt), the=20
PLPRCR register show us the event and the procedure timer_interrupt() cle=
ans=20
the TMIST & TEXP flags. =20

If another interrupt were enable, for example (Periodic Timer Expires,=20
Real-Time clock alarm sets, timebase clock alarm sets, etc).   another ro=
utine
should clean this flags, but we couldn't find anyone =BFThere are another=
 ones?

We think it's designed just for let the DECREMENTER interrupt to happen
because we have seen that the timer interrupt are disables by Software.
=BFCould an interrupt routine (diferent of DECREMENTER) access the proced=
ure
timer_interrupt()?

* The development board use the next hardware:
    FLASH   8 MB   AM29LV160DB      CS0, CS1      Controlled by GPCM
    RAM     16 MB   48LC4M16A2        CS2              Controlled by UPMA
    PCMCIA
    50 Mhz clock


In our system we don't have a 32Khz crystal,  We know the loader is desig=
ned
to work with one.  =20
We disable it by adding #define CONFIG_8xx_GCLK_FREQ 50000000.

We disable the Real Time Clock
 #define CONFIG_RTC_MPC8xx      by  #undef CONFIG_RTC_MPC8xx
 #define RTCSC                             by  #undef RTCSC,


When there is not a 32khz crystal, =BFis needed to define RTCSC?   I ask =
it,
because the output of the PITRTCLK change from 8.192 khz to 97.6 Khz
(RTSEL=3D1,RTDIV=3D1), and the Real Time Clock can just select
between 32k and 37.8k We found that in  cpu/mpc8xx/cpu_init.c
is defined the function CPU_INIT_R and it uses RTCSC


cpu_init_r  (bd_t *bd)
{
#if defined(CFG_RTCSC) || defined(CFG_RMDS)
    volatile immap_t *immr =3D (volatile immap_t *)(bd->bi_immr_base);


In the STK8xx the TEXP pin (X6 port) should show the interrupts events (b=
y a
change in there signal 1->0) but in our test in 100 Mhz scope, there was =
no
signal variations.  What could this mean?



To monitor de Decrementer interrupt we added code (it write a 1 and then =
a 0
in the timer_interrupt() routine)  The STK8xx shows it at regular interva=
ls
but our system shows an erratic behabior at the same speed.
When it's set to 1.25ms, 2ms, 4ms, so on in the IDLE state (bootloader
ejecuting and showing the console) the times are regular at setting
intervals, but when a MTEST is execute the time is up (1 - just inside th=
e
timer_interrupt routine) could be until 0.25ms.


Were discarded:
   Energy problem.
   Oscilator Frecuency Problem.
   PLL - VCO problem.
   Clock problem, the DEC timming for 1.25 to 16ms works OK.


What this problem cause:
   Although we work in the loader enviroment, when we try to write a
     Linux-Kernel in the Flash it failed for timeout.  We couldn't even w=
rite
   the Hello_World.srec that come in the loader distribution (ppcboot-1.1=
=2E0)